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										 |  |  | #ifndef __ASM_SH_AUXVEC_H
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							|  |  |  | #define __ASM_SH_AUXVEC_H
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											2006-09-27 18:33:49 +09:00
										 |  |  | /*
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							|  |  |  |  * Architecture-neutral AT_ values in 0-17, leave some room | 
					
						
							|  |  |  |  * for more of them. | 
					
						
							|  |  |  |  */ | 
					
						
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											2007-12-10 16:21:57 +09:00
										 |  |  | /*
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							|  |  |  |  * This entry gives some information about the FPU initialization | 
					
						
							|  |  |  |  * performed by the kernel. | 
					
						
							|  |  |  |  */ | 
					
						
							|  |  |  | #define AT_FPUCW		18	/* Used FPU control word.  */
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										 |  |  | #if defined(CONFIG_VSYSCALL) || !defined(__KERNEL__)
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										 |  |  | /*
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							|  |  |  |  * Only define this in the vsyscall case, the entry point to | 
					
						
							|  |  |  |  * the vsyscall page gets placed here. The kernel will attempt | 
					
						
							|  |  |  |  * to build a gate VMA we don't care about otherwise.. | 
					
						
							|  |  |  |  */ | 
					
						
							|  |  |  | #define AT_SYSINFO_EHDR		33
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							|  |  |  | #endif
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											2007-12-10 15:50:28 +09:00
										 |  |  | /*
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							|  |  |  |  * More complete cache descriptions than AT_[DIU]CACHEBSIZE.  If the | 
					
						
							|  |  |  |  * value is -1, then the cache doesn't exist.  Otherwise: | 
					
						
							|  |  |  |  * | 
					
						
							|  |  |  |  *    bit 0-3:	  Cache set-associativity; 0 means fully associative. | 
					
						
							|  |  |  |  *    bit 4-7:	  Log2 of cacheline size. | 
					
						
							|  |  |  |  *    bit 8-31:	  Size of the entire cache >> 8. | 
					
						
							|  |  |  |  */ | 
					
						
							|  |  |  | #define AT_L1I_CACHESHAPE	34
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							|  |  |  | #define AT_L1D_CACHESHAPE	35
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							|  |  |  | #define AT_L2_CACHESHAPE	36
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										 |  |  | #define AT_VECTOR_SIZE_ARCH 5 /* entries in ARCH_DLINFO */
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											2005-09-06 15:16:49 -07:00
										 |  |  | #endif /* __ASM_SH_AUXVEC_H */
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