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linux-pinenote/arch/powerpc/boot/dts/mpc8572ds_36b.dts

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powerpc/85xx: Added 36-bit physical device tree for mpc8572ds board Added a device tree that should be identical to mpc8572ds.dtb except the physical addresses for all IO are above the 4G boundary. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-02-09 21:39:31 -06:00
/*
powerpc/85xx: Rework MPC8572DS device tree Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Removed CPU properties setup by u-boot to match other .dts * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Moved mdio nodes up one level instead of under tsec nodes * Added GPIO controller node to MPC8572 SoC template * Dropping "fsl,mpc8572-IP..." from compatibles for standard blocks Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-03 01:07:56 -05:00
* MPC8572DS Device Tree Source (36-bit address map)
powerpc/85xx: Added 36-bit physical device tree for mpc8572ds board Added a device tree that should be identical to mpc8572ds.dtb except the physical addresses for all IO are above the 4G boundary. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-02-09 21:39:31 -06:00
*
* Copyright 2007-2009 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
powerpc/85xx: Rework MPC8572DS device tree Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Removed CPU properties setup by u-boot to match other .dts * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Moved mdio nodes up one level instead of under tsec nodes * Added GPIO controller node to MPC8572 SoC template * Dropping "fsl,mpc8572-IP..." from compatibles for standard blocks Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-03 01:07:56 -05:00
/include/ "fsl/mpc8572si-pre.dtsi"
powerpc/85xx: Added 36-bit physical device tree for mpc8572ds board Added a device tree that should be identical to mpc8572ds.dtb except the physical addresses for all IO are above the 4G boundary. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-02-09 21:39:31 -06:00
/ {
model = "fsl,MPC8572DS";
compatible = "fsl,MPC8572DS";
memory {
device_type = "memory";
};
powerpc/85xx: Rework MPC8572DS device tree Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Removed CPU properties setup by u-boot to match other .dts * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Moved mdio nodes up one level instead of under tsec nodes * Added GPIO controller node to MPC8572 SoC template * Dropping "fsl,mpc8572-IP..." from compatibles for standard blocks Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-03 01:07:56 -05:00
board_lbc: lbc: localbus@fffe05000 {
powerpc/85xx: Added 36-bit physical device tree for mpc8572ds board Added a device tree that should be identical to mpc8572ds.dtb except the physical addresses for all IO are above the 4G boundary. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-02-09 21:39:31 -06:00
reg = <0xf 0xffe05000 0 0x1000>;
ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
0x1 0x0 0xf 0xe0000000 0x08000000
0x2 0x0 0xf 0xffa00000 0x00040000
0x3 0x0 0xf 0xffdf0000 0x00008000
0x4 0x0 0xf 0xffa40000 0x00040000
0x5 0x0 0xf 0xffa80000 0x00040000
0x6 0x0 0xf 0xffac0000 0x00040000>;
};
powerpc/85xx: Rework MPC8572DS device tree Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Removed CPU properties setup by u-boot to match other .dts * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Moved mdio nodes up one level instead of under tsec nodes * Added GPIO controller node to MPC8572 SoC template * Dropping "fsl,mpc8572-IP..." from compatibles for standard blocks Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-03 01:07:56 -05:00
board_soc: soc: soc8572@fffe00000 {
powerpc/85xx: Added 36-bit physical device tree for mpc8572ds board Added a device tree that should be identical to mpc8572ds.dtb except the physical addresses for all IO are above the 4G boundary. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-02-09 21:39:31 -06:00
ranges = <0x0 0xf 0xffe00000 0x100000>;
};
powerpc/85xx: Rework MPC8572DS device tree Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Removed CPU properties setup by u-boot to match other .dts * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Moved mdio nodes up one level instead of under tsec nodes * Added GPIO controller node to MPC8572 SoC template * Dropping "fsl,mpc8572-IP..." from compatibles for standard blocks Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-03 01:07:56 -05:00
board_pci0: pci0: pcie@fffe08000 {
powerpc/85xx: Added 36-bit physical device tree for mpc8572ds board Added a device tree that should be identical to mpc8572ds.dtb except the physical addresses for all IO are above the 4G boundary. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-02-09 21:39:31 -06:00
reg = <0xf 0xffe08000 0 0x1000>;
powerpc/8xxx: Update PCI outbound window addresses for 36-bit configs In these configuration we expect to have large amounts of memory (> 4G) and thus will bounce via swiotlb some region of PCI address space. The outbound windows were wasting 512M of address space by leaving a gap between the top of the outbound window and the 4G boundary. By moving the top of the outbound window up to the 4G boundary we can reclaim the vast majority of the 512M (minus space needed for PEXCSRBAR) and thus reduces the amount of memory we have to bounce. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-05-12 16:59:12 -05:00
ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000
powerpc/85xx: Added 36-bit physical device tree for mpc8572ds board Added a device tree that should be identical to mpc8572ds.dtb except the physical addresses for all IO are above the 4G boundary. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-02-09 21:39:31 -06:00
0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000>;
pcie@0 {
powerpc/8xxx: Update PCI outbound window addresses for 36-bit configs In these configuration we expect to have large amounts of memory (> 4G) and thus will bounce via swiotlb some region of PCI address space. The outbound windows were wasting 512M of address space by leaving a gap between the top of the outbound window and the 4G boundary. By moving the top of the outbound window up to the 4G boundary we can reclaim the vast majority of the 512M (minus space needed for PEXCSRBAR) and thus reduces the amount of memory we have to bounce. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-05-12 16:59:12 -05:00
ranges = <0x2000000 0x0 0xe0000000
0x2000000 0x0 0xe0000000
powerpc/85xx: Added 36-bit physical device tree for mpc8572ds board Added a device tree that should be identical to mpc8572ds.dtb except the physical addresses for all IO are above the 4G boundary. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-02-09 21:39:31 -06:00
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x10000>;
};
};
pci1: pcie@fffe09000 {
reg = <0xf 0xffe09000 0 0x1000>;
powerpc/8xxx: Update PCI outbound window addresses for 36-bit configs In these configuration we expect to have large amounts of memory (> 4G) and thus will bounce via swiotlb some region of PCI address space. The outbound windows were wasting 512M of address space by leaving a gap between the top of the outbound window and the 4G boundary. By moving the top of the outbound window up to the 4G boundary we can reclaim the vast majority of the 512M (minus space needed for PEXCSRBAR) and thus reduces the amount of memory we have to bounce. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-05-12 16:59:12 -05:00
ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
powerpc/85xx: Added 36-bit physical device tree for mpc8572ds board Added a device tree that should be identical to mpc8572ds.dtb except the physical addresses for all IO are above the 4G boundary. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-02-09 21:39:31 -06:00
0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x00010000>;
pcie@0 {
powerpc/8xxx: Update PCI outbound window addresses for 36-bit configs In these configuration we expect to have large amounts of memory (> 4G) and thus will bounce via swiotlb some region of PCI address space. The outbound windows were wasting 512M of address space by leaving a gap between the top of the outbound window and the 4G boundary. By moving the top of the outbound window up to the 4G boundary we can reclaim the vast majority of the 512M (minus space needed for PEXCSRBAR) and thus reduces the amount of memory we have to bounce. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-05-12 16:59:12 -05:00
ranges = <0x2000000 0x0 0xe0000000
0x2000000 0x0 0xe0000000
powerpc/85xx: Added 36-bit physical device tree for mpc8572ds board Added a device tree that should be identical to mpc8572ds.dtb except the physical addresses for all IO are above the 4G boundary. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-02-09 21:39:31 -06:00
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x10000>;
};
};
pci2: pcie@fffe0a000 {
reg = <0xf 0xffe0a000 0 0x1000>;
powerpc/8xxx: Update PCI outbound window addresses for 36-bit configs In these configuration we expect to have large amounts of memory (> 4G) and thus will bounce via swiotlb some region of PCI address space. The outbound windows were wasting 512M of address space by leaving a gap between the top of the outbound window and the 4G boundary. By moving the top of the outbound window up to the 4G boundary we can reclaim the vast majority of the 512M (minus space needed for PEXCSRBAR) and thus reduces the amount of memory we have to bounce. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-05-12 16:59:12 -05:00
ranges = <0x2000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000
powerpc/85xx: Added 36-bit physical device tree for mpc8572ds board Added a device tree that should be identical to mpc8572ds.dtb except the physical addresses for all IO are above the 4G boundary. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-02-09 21:39:31 -06:00
0x1000000 0x0 0x00000000 0xf 0xffc20000 0x0 0x00010000>;
pcie@0 {
powerpc/8xxx: Update PCI outbound window addresses for 36-bit configs In these configuration we expect to have large amounts of memory (> 4G) and thus will bounce via swiotlb some region of PCI address space. The outbound windows were wasting 512M of address space by leaving a gap between the top of the outbound window and the 4G boundary. By moving the top of the outbound window up to the 4G boundary we can reclaim the vast majority of the 512M (minus space needed for PEXCSRBAR) and thus reduces the amount of memory we have to bounce. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-05-12 16:59:12 -05:00
ranges = <0x2000000 0x0 0xe0000000
0x2000000 0x0 0xe0000000
powerpc/85xx: Added 36-bit physical device tree for mpc8572ds board Added a device tree that should be identical to mpc8572ds.dtb except the physical addresses for all IO are above the 4G boundary. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-02-09 21:39:31 -06:00
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x10000>;
};
};
};
powerpc/85xx: Rework MPC8572DS device tree Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Removed CPU properties setup by u-boot to match other .dts * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Moved mdio nodes up one level instead of under tsec nodes * Added GPIO controller node to MPC8572 SoC template * Dropping "fsl,mpc8572-IP..." from compatibles for standard blocks Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-03 01:07:56 -05:00
/*
* mpc8572ds.dtsi must be last to ensure board_pci0 overrides pci0 settings
* for interrupt-map & interrupt-map-mask
*/
/include/ "fsl/mpc8572si-post.dtsi"
/include/ "mpc8572ds.dtsi"
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