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								/* arch/arm/mach-s3c2410/include/mach/regs-irq.h
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								 *
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								 * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
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								 *		      http://www.simtec.co.uk/products/SWLINUX/
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								 *
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								 * This program is free software; you can redistribute it and/or modify
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								 * it under the terms of the GNU General Public License version 2 as
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								 * published by the Free Software Foundation.
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								*/
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								#ifndef ___ASM_ARCH_REGS_IRQ_H
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								#define ___ASM_ARCH_REGS_IRQ_H
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								/* interrupt controller */
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								#define S3C2410_IRQREG(x)   ((x) + S3C24XX_VA_IRQ)
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								#define S3C2410_EINTREG(x)  ((x) + S3C24XX_VA_GPIO)
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								#define S3C24XX_EINTREG(x)  ((x) + S3C24XX_VA_GPIO2)
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								#define S3C2410_SRCPND	       S3C2410_IRQREG(0x000)
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								#define S3C2410_INTMOD	       S3C2410_IRQREG(0x004)
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								#define S3C2410_INTMSK	       S3C2410_IRQREG(0x008)
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								#define S3C2410_PRIORITY       S3C2410_IRQREG(0x00C)
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								#define S3C2410_INTPND	       S3C2410_IRQREG(0x010)
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								#define S3C2410_INTOFFSET      S3C2410_IRQREG(0x014)
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								#define S3C2410_SUBSRCPND      S3C2410_IRQREG(0x018)
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								#define S3C2410_INTSUBMSK      S3C2410_IRQREG(0x01C)
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								#define S3C2416_PRIORITY_MODE1		S3C2410_IRQREG(0x030)
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								#define S3C2416_PRIORITY_UPDATE1	S3C2410_IRQREG(0x034)
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								#define S3C2416_SRCPND2			S3C2410_IRQREG(0x040)
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								#define S3C2416_INTMOD2			S3C2410_IRQREG(0x044)
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								#define S3C2416_INTMSK2			S3C2410_IRQREG(0x048)
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								#define S3C2416_INTPND2			S3C2410_IRQREG(0x050)
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								#define S3C2416_INTOFFSET2		S3C2410_IRQREG(0x054)
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								#define S3C2416_PRIORITY_MODE2		S3C2410_IRQREG(0x070)
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								#define S3C2416_PRIORITY_UPDATE2	S3C2410_IRQREG(0x074)
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								/* mask: 0=enable, 1=disable
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								 * 1 bit EINT, 4=EINT4, 23=EINT23
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								 * EINT0,1,2,3 are not handled here.
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								*/
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								#define S3C2410_EINTMASK       S3C2410_EINTREG(0x0A4)
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								#define S3C2410_EINTPEND       S3C2410_EINTREG(0X0A8)
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								#define S3C2412_EINTMASK       S3C2410_EINTREG(0x0B4)
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								#define S3C2412_EINTPEND       S3C2410_EINTREG(0X0B8)
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								#define S3C24XX_EINTMASK       S3C24XX_EINTREG(0x0A4)
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								#define S3C24XX_EINTPEND       S3C24XX_EINTREG(0X0A8)
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								#endif /* ___ASM_ARCH_REGS_IRQ_H */
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