135 lines
2.6 KiB
Text
135 lines
2.6 KiB
Text
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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reg = <0>;
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model = "ti,c64x+";
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};
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cpu@1 {
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device_type = "cpu";
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reg = <1>;
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model = "ti,c64x+";
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};
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cpu@2 {
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device_type = "cpu";
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reg = <2>;
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model = "ti,c64x+";
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};
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cpu@3 {
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device_type = "cpu";
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reg = <3>;
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model = "ti,c64x+";
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};
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cpu@4 {
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device_type = "cpu";
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reg = <4>;
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model = "ti,c64x+";
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};
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cpu@5 {
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device_type = "cpu";
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reg = <5>;
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model = "ti,c64x+";
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};
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};
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soc {
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compatible = "simple-bus";
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model = "tms320c6472";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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core_pic: interrupt-controller {
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compatible = "ti,c64x+core-pic";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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megamod_pic: interrupt-controller@1800000 {
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compatible = "ti,c64x+megamod-pic";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x1800000 0x1000>;
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interrupt-parent = <&core_pic>;
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};
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cache-controller@1840000 {
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compatible = "ti,c64x+cache";
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reg = <0x01840000 0x8400>;
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};
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timer0: timer@25e0000 {
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compatible = "ti,c64x+timer64";
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ti,core-mask = < 0x01 >;
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reg = <0x25e0000 0x40>;
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};
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timer1: timer@25f0000 {
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compatible = "ti,c64x+timer64";
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ti,core-mask = < 0x02 >;
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reg = <0x25f0000 0x40>;
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};
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timer2: timer@2600000 {
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compatible = "ti,c64x+timer64";
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ti,core-mask = < 0x04 >;
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reg = <0x2600000 0x40>;
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};
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timer3: timer@2610000 {
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compatible = "ti,c64x+timer64";
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ti,core-mask = < 0x08 >;
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reg = <0x2610000 0x40>;
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};
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timer4: timer@2620000 {
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compatible = "ti,c64x+timer64";
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ti,core-mask = < 0x10 >;
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reg = <0x2620000 0x40>;
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};
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timer5: timer@2630000 {
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compatible = "ti,c64x+timer64";
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ti,core-mask = < 0x20 >;
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reg = <0x2630000 0x40>;
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};
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clock-controller@29a0000 {
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compatible = "ti,c6472-pll", "ti,c64x+pll";
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reg = <0x029a0000 0x200>;
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ti,c64x+pll-bypass-delay = <200>;
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ti,c64x+pll-reset-delay = <12000>;
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ti,c64x+pll-lock-delay = <80000>;
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};
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device-state-controller@2a80000 {
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compatible = "ti,c64x+dscr";
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reg = <0x02a80000 0x1000>;
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ti,dscr-devstat = <0>;
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ti,dscr-silicon-rev = <0x70c 16 0xff>;
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ti,dscr-mac-fuse-regs = <0x700 1 2 3 4
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0x704 5 6 0 0>;
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ti,dscr-rmii-resets = <0x208 1
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0x20c 1>;
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ti,dscr-locked-regs = <0x200 0x204 0x0a1e183a
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0x40c 0x420 0xbea7
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0x41c 0x420 0xbea7>;
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ti,dscr-privperm = <0x41c 0xaaaaaaaa>;
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ti,dscr-devstate-ctl-regs = <0 13 0x200 1 0 0 1>;
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};
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};
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};
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