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										 |  |  | #ifndef _ASM_POWERPC_MMU_FSL_BOOKE_H_
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							|  |  |  | #define _ASM_POWERPC_MMU_FSL_BOOKE_H_
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							|  |  |  | /*
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							|  |  |  |  * Freescale Book-E MMU support | 
					
						
							|  |  |  |  */ | 
					
						
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							|  |  |  | /* Book-E defined page sizes */ | 
					
						
							|  |  |  | #define BOOKE_PAGESZ_1K		0
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							|  |  |  | #define BOOKE_PAGESZ_4K		1
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							|  |  |  | #define BOOKE_PAGESZ_16K	2
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							|  |  |  | #define BOOKE_PAGESZ_64K	3
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							|  |  |  | #define BOOKE_PAGESZ_256K	4
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							|  |  |  | #define BOOKE_PAGESZ_1M		5
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							|  |  |  | #define BOOKE_PAGESZ_4M		6
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							|  |  |  | #define BOOKE_PAGESZ_16M	7
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							|  |  |  | #define BOOKE_PAGESZ_64M	8
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							|  |  |  | #define BOOKE_PAGESZ_256M	9
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							|  |  |  | #define BOOKE_PAGESZ_1GB	10
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							|  |  |  | #define BOOKE_PAGESZ_4GB	11
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							|  |  |  | #define BOOKE_PAGESZ_16GB	12
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							|  |  |  | #define BOOKE_PAGESZ_64GB	13
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							|  |  |  | #define BOOKE_PAGESZ_256GB	14
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							|  |  |  | #define BOOKE_PAGESZ_1TB	15
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							|  |  |  | #define MAS0_TLBSEL(x)	((x << 28) & 0x30000000)
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							|  |  |  | #define MAS0_ESEL(x)	((x << 16) & 0x0FFF0000)
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							|  |  |  | #define MAS0_NV(x)	((x) & 0x00000FFF)
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							|  |  |  | 
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							|  |  |  | #define MAS1_VALID 	0x80000000
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							|  |  |  | #define MAS1_IPROT	0x40000000
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							|  |  |  | #define MAS1_TID(x)	((x << 16) & 0x3FFF0000)
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							|  |  |  | #define MAS1_TS		0x00001000
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							|  |  |  | #define MAS1_TSIZE(x)	((x << 8) & 0x00000F00)
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							|  |  |  | #define MAS2_EPN	0xFFFFF000
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							|  |  |  | #define MAS2_X0		0x00000040
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							|  |  |  | #define MAS2_X1		0x00000020
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							|  |  |  | #define MAS2_W		0x00000010
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							|  |  |  | #define MAS2_I		0x00000008
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							|  |  |  | #define MAS2_M		0x00000004
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							|  |  |  | #define MAS2_G		0x00000002
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							|  |  |  | #define MAS2_E		0x00000001
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							| 
									
										
											  
											
												powerpc: Better setup of boot page TLB entry
The initial TLB mapping for the kernel boot didn't set the memory coherent
attribute, MAS2[M], in SMP mode.
If this code supported booting a secondary processor, which it doesn't yet,
but if it did, then when a secondary processor boots, it would probably signal
the primary processor by setting a variable called something like
__secondary_hold_acknowledge.  However, due to the lack of the M bit, the
primary processor would not snoop the transaction (even if a transaction were
broadcast).  If primary CPU's L1 D-cache had a copy, it would not be flushed
and the CPU would never see the ack.  Which would have resulted in the primary
CPU spinning for a long time, perhaps a full second before it gives up, while
it would have waited for the ack from the secondary CPU that it wouldn't have
been able to see because of the stale cache.
The value of MAS2 for the boot page TLB1 entry is a compile time constant,
so there is no need to calculate it in powerpc assembly language.
Also, from the MPC8572 manual section 6.12.5.3, "Bits that represent
offsets within a page are ignored and should be cleared." Existing code
didn't clear them, this code does.
The same when the page of KERNELBASE is found; we don't need to use asm to
mask the lower 12 bits off.
In the code that computes the address to rfi from, don't hard code the
offset to 24 bytes, but have the assembler figure that out for us.
Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
											
										 
											2008-11-19 03:13:14 -08:00
										 |  |  | #define MAS2_EPN_MASK(size)		(~0 << (2*(size) + 10))
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							|  |  |  | #define MAS2_VAL(addr, size, flags)	((addr) & MAS2_EPN_MASK(size) | (flags))
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										 |  |  | 
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							|  |  |  | #define MAS3_RPN	0xFFFFF000
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							|  |  |  | #define MAS3_U0		0x00000200
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							|  |  |  | #define MAS3_U1		0x00000100
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							|  |  |  | #define MAS3_U2		0x00000080
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							|  |  |  | #define MAS3_U3		0x00000040
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							|  |  |  | #define MAS3_UX		0x00000020
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							|  |  |  | #define MAS3_SX		0x00000010
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							|  |  |  | #define MAS3_UW		0x00000008
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							|  |  |  | #define MAS3_SW		0x00000004
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							|  |  |  | #define MAS3_UR		0x00000002
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							|  |  |  | #define MAS3_SR		0x00000001
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							|  |  |  | #define MAS4_TLBSELD(x) MAS0_TLBSEL(x)
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							|  |  |  | #define MAS4_TIDDSEL	0x000F0000
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							|  |  |  | #define MAS4_TSIZED(x)	MAS1_TSIZE(x)
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							|  |  |  | #define MAS4_X0D	0x00000040
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							|  |  |  | #define MAS4_X1D	0x00000020
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							|  |  |  | #define MAS4_WD		0x00000010
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							|  |  |  | #define MAS4_ID		0x00000008
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							|  |  |  | #define MAS4_MD		0x00000004
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							|  |  |  | #define MAS4_GD		0x00000002
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							|  |  |  | #define MAS4_ED		0x00000001
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							|  |  |  | #define MAS6_SPID0	0x3FFF0000
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							|  |  |  | #define MAS6_SPID1	0x00007FFE
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							|  |  |  | #define MAS6_SAS	0x00000001
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							|  |  |  | #define MAS6_SPID	MAS6_SPID0
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							|  |  |  | #define MAS7_RPN	0xFFFFFFFF
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							|  |  |  | #ifndef __ASSEMBLY__
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							|  |  |  | typedef struct { | 
					
						
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										 |  |  | 	unsigned int	id; | 
					
						
							|  |  |  | 	unsigned int	active; | 
					
						
							|  |  |  | 	unsigned long	vdso_base; | 
					
						
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										 |  |  | } mm_context_t; | 
					
						
							|  |  |  | #endif /* !__ASSEMBLY__ */
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							|  |  |  | #endif /* _ASM_POWERPC_MMU_FSL_BOOKE_H_ */
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