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										 |  |  | /* | 
					
						
							|  |  |  |  * MPC8540 ADS Device Tree Source | 
					
						
							|  |  |  |  * | 
					
						
							| 
									
										
										
										
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										 |  |  |  * Copyright 2006, 2008 Freescale Semiconductor Inc. | 
					
						
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										 |  |  |  * | 
					
						
							|  |  |  |  * This program is free software; you can redistribute  it and/or modify it | 
					
						
							|  |  |  |  * under  the terms of  the GNU General  Public License as published by the | 
					
						
							|  |  |  |  * Free Software Foundation;  either version 2 of the  License, or (at your | 
					
						
							|  |  |  |  * option) any later version. | 
					
						
							|  |  |  |  */ | 
					
						
							|  |  |  | 
 | 
					
						
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										 |  |  | /dts-v1/; | 
					
						
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										 |  |  | 
 | 
					
						
							|  |  |  | / { | 
					
						
							|  |  |  | 	model = "MPC8540ADS"; | 
					
						
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										 |  |  | 	compatible = "MPC8540ADS", "MPC85xxADS"; | 
					
						
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										 |  |  | 	#address-cells = <1>; | 
					
						
							|  |  |  | 	#size-cells = <1>; | 
					
						
							|  |  |  | 
 | 
					
						
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										 |  |  | 	aliases { | 
					
						
							|  |  |  | 		ethernet0 = &enet0; | 
					
						
							|  |  |  | 		ethernet1 = &enet1; | 
					
						
							|  |  |  | 		ethernet2 = &enet2; | 
					
						
							|  |  |  | 		serial0 = &serial0; | 
					
						
							|  |  |  | 		serial1 = &serial1; | 
					
						
							|  |  |  | 		pci0 = &pci0; | 
					
						
							|  |  |  | 	}; | 
					
						
							|  |  |  | 
 | 
					
						
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										 |  |  | 	cpus { | 
					
						
							|  |  |  | 		#address-cells = <1>; | 
					
						
							|  |  |  | 		#size-cells = <0>; | 
					
						
							|  |  |  | 
 | 
					
						
							|  |  |  | 		PowerPC,8540@0 { | 
					
						
							|  |  |  | 			device_type = "cpu"; | 
					
						
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										 |  |  | 			reg = <0x0>; | 
					
						
							|  |  |  | 			d-cache-line-size = <32>;	// 32 bytes | 
					
						
							|  |  |  | 			i-cache-line-size = <32>;	// 32 bytes | 
					
						
							|  |  |  | 			d-cache-size = <0x8000>;		// L1, 32K | 
					
						
							|  |  |  | 			i-cache-size = <0x8000>;		// L1, 32K | 
					
						
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										 |  |  | 			timebase-frequency = <0>;	//  33 MHz, from uboot | 
					
						
							|  |  |  | 			bus-frequency = <0>;	// 166 MHz | 
					
						
							|  |  |  | 			clock-frequency = <0>;	// 825 MHz, from uboot | 
					
						
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										 |  |  | 			next-level-cache = <&L2>; | 
					
						
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										 |  |  | 		}; | 
					
						
							|  |  |  | 	}; | 
					
						
							|  |  |  | 
 | 
					
						
							|  |  |  | 	memory { | 
					
						
							|  |  |  | 		device_type = "memory"; | 
					
						
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										 |  |  | 		reg = <0x0 0x8000000>;	// 128M at 0x0 | 
					
						
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										 |  |  | 	}; | 
					
						
							|  |  |  | 
 | 
					
						
							|  |  |  | 	soc8540@e0000000 { | 
					
						
							|  |  |  | 		#address-cells = <1>; | 
					
						
							|  |  |  | 		#size-cells = <1>; | 
					
						
							|  |  |  | 		device_type = "soc"; | 
					
						
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										 |  |  | 		compatible = "simple-bus"; | 
					
						
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										 |  |  | 		ranges = <0x0 0xe0000000 0x100000>; | 
					
						
							|  |  |  | 		reg = <0xe0000000 0x100000>;	// CCSRBAR 1M | 
					
						
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										 |  |  | 		bus-frequency = <0>; | 
					
						
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 | 
					
						
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										 |  |  | 		memory-controller@2000 { | 
					
						
							|  |  |  | 			compatible = "fsl,8540-memory-controller"; | 
					
						
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										 |  |  | 			reg = <0x2000 0x1000>; | 
					
						
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										 |  |  | 			interrupt-parent = <&mpic>; | 
					
						
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										 |  |  | 			interrupts = <18 2>; | 
					
						
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										 |  |  | 		}; | 
					
						
							|  |  |  | 
 | 
					
						
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										 |  |  | 		L2: l2-cache-controller@20000 { | 
					
						
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										 |  |  | 			compatible = "fsl,8540-l2-cache-controller"; | 
					
						
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										 |  |  | 			reg = <0x20000 0x1000>; | 
					
						
							|  |  |  | 			cache-line-size = <32>;	// 32 bytes | 
					
						
							|  |  |  | 			cache-size = <0x40000>;	// L2, 256K | 
					
						
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										 |  |  | 			interrupt-parent = <&mpic>; | 
					
						
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										 |  |  | 			interrupts = <16 2>; | 
					
						
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										 |  |  | 		}; | 
					
						
							|  |  |  | 
 | 
					
						
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										 |  |  | 		i2c@3000 { | 
					
						
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										 |  |  | 			#address-cells = <1>; | 
					
						
							|  |  |  | 			#size-cells = <0>; | 
					
						
							|  |  |  | 			cell-index = <0>; | 
					
						
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										 |  |  | 			compatible = "fsl-i2c"; | 
					
						
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										 |  |  | 			reg = <0x3000 0x100>; | 
					
						
							|  |  |  | 			interrupts = <43 2>; | 
					
						
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										 |  |  | 			interrupt-parent = <&mpic>; | 
					
						
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										 |  |  | 			dfsrr; | 
					
						
							|  |  |  | 		}; | 
					
						
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										 |  |  | 		dma@21300 { | 
					
						
							|  |  |  | 			#address-cells = <1>; | 
					
						
							|  |  |  | 			#size-cells = <1>; | 
					
						
							|  |  |  | 			compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma"; | 
					
						
							|  |  |  | 			reg = <0x21300 0x4>; | 
					
						
							|  |  |  | 			ranges = <0x0 0x21100 0x200>; | 
					
						
							|  |  |  | 			cell-index = <0>; | 
					
						
							|  |  |  | 			dma-channel@0 { | 
					
						
							|  |  |  | 				compatible = "fsl,mpc8540-dma-channel", | 
					
						
							|  |  |  | 						"fsl,eloplus-dma-channel"; | 
					
						
							|  |  |  | 				reg = <0x0 0x80>; | 
					
						
							|  |  |  | 				cell-index = <0>; | 
					
						
							|  |  |  | 				interrupt-parent = <&mpic>; | 
					
						
							|  |  |  | 				interrupts = <20 2>; | 
					
						
							|  |  |  | 			}; | 
					
						
							|  |  |  | 			dma-channel@80 { | 
					
						
							|  |  |  | 				compatible = "fsl,mpc8540-dma-channel", | 
					
						
							|  |  |  | 						"fsl,eloplus-dma-channel"; | 
					
						
							|  |  |  | 				reg = <0x80 0x80>; | 
					
						
							|  |  |  | 				cell-index = <1>; | 
					
						
							|  |  |  | 				interrupt-parent = <&mpic>; | 
					
						
							|  |  |  | 				interrupts = <21 2>; | 
					
						
							|  |  |  | 			}; | 
					
						
							|  |  |  | 			dma-channel@100 { | 
					
						
							|  |  |  | 				compatible = "fsl,mpc8540-dma-channel", | 
					
						
							|  |  |  | 						"fsl,eloplus-dma-channel"; | 
					
						
							|  |  |  | 				reg = <0x100 0x80>; | 
					
						
							|  |  |  | 				cell-index = <2>; | 
					
						
							|  |  |  | 				interrupt-parent = <&mpic>; | 
					
						
							|  |  |  | 				interrupts = <22 2>; | 
					
						
							|  |  |  | 			}; | 
					
						
							|  |  |  | 			dma-channel@180 { | 
					
						
							|  |  |  | 				compatible = "fsl,mpc8540-dma-channel", | 
					
						
							|  |  |  | 						"fsl,eloplus-dma-channel"; | 
					
						
							|  |  |  | 				reg = <0x180 0x80>; | 
					
						
							|  |  |  | 				cell-index = <3>; | 
					
						
							|  |  |  | 				interrupt-parent = <&mpic>; | 
					
						
							|  |  |  | 				interrupts = <23 2>; | 
					
						
							|  |  |  | 			}; | 
					
						
							|  |  |  | 		}; | 
					
						
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 | 
					
						
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										 |  |  | 		mdio@24520 { | 
					
						
							|  |  |  | 			#address-cells = <1>; | 
					
						
							|  |  |  | 			#size-cells = <0>; | 
					
						
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										 |  |  | 			compatible = "fsl,gianfar-mdio"; | 
					
						
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										 |  |  | 			reg = <0x24520 0x20>; | 
					
						
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										 |  |  | 
 | 
					
						
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										 |  |  | 			phy0: ethernet-phy@0 { | 
					
						
							|  |  |  | 				interrupt-parent = <&mpic>; | 
					
						
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										 |  |  | 				interrupts = <5 1>; | 
					
						
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										 |  |  | 				reg = <0x0>; | 
					
						
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										 |  |  | 				device_type = "ethernet-phy"; | 
					
						
							|  |  |  | 			}; | 
					
						
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										 |  |  | 			phy1: ethernet-phy@1 { | 
					
						
							|  |  |  | 				interrupt-parent = <&mpic>; | 
					
						
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										 |  |  | 				interrupts = <5 1>; | 
					
						
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										 |  |  | 				reg = <0x1>; | 
					
						
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										 |  |  | 				device_type = "ethernet-phy"; | 
					
						
							|  |  |  | 			}; | 
					
						
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										 |  |  | 			phy3: ethernet-phy@3 { | 
					
						
							|  |  |  | 				interrupt-parent = <&mpic>; | 
					
						
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										 |  |  | 				interrupts = <7 1>; | 
					
						
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										 |  |  | 				reg = <0x3>; | 
					
						
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										 |  |  | 				device_type = "ethernet-phy"; | 
					
						
							|  |  |  | 			}; | 
					
						
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										 |  |  | 			tbi0: tbi-phy@11 { | 
					
						
							|  |  |  | 				reg = <0x11>; | 
					
						
							|  |  |  | 				device_type = "tbi-phy"; | 
					
						
							|  |  |  | 			}; | 
					
						
							|  |  |  | 		}; | 
					
						
							|  |  |  | 
 | 
					
						
							|  |  |  | 		mdio@25520 { | 
					
						
							|  |  |  | 			#address-cells = <1>; | 
					
						
							|  |  |  | 			#size-cells = <0>; | 
					
						
							|  |  |  | 			compatible = "fsl,gianfar-tbi"; | 
					
						
							|  |  |  | 			reg = <0x25520 0x20>; | 
					
						
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 | 
					
						
							|  |  |  | 			tbi1: tbi-phy@11 { | 
					
						
							|  |  |  | 				reg = <0x11>; | 
					
						
							|  |  |  | 				device_type = "tbi-phy"; | 
					
						
							|  |  |  | 			}; | 
					
						
							|  |  |  | 		}; | 
					
						
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 | 
					
						
							|  |  |  | 		mdio@26520 { | 
					
						
							|  |  |  | 			#address-cells = <1>; | 
					
						
							|  |  |  | 			#size-cells = <0>; | 
					
						
							|  |  |  | 			compatible = "fsl,gianfar-tbi"; | 
					
						
							|  |  |  | 			reg = <0x26520 0x20>; | 
					
						
							|  |  |  | 
 | 
					
						
							|  |  |  | 			tbi2: tbi-phy@11 { | 
					
						
							|  |  |  | 				reg = <0x11>; | 
					
						
							|  |  |  | 				device_type = "tbi-phy"; | 
					
						
							|  |  |  | 			}; | 
					
						
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										 |  |  | 		}; | 
					
						
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 | 
					
						
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										 |  |  | 		enet0: ethernet@24000 { | 
					
						
							|  |  |  | 			cell-index = <0>; | 
					
						
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										 |  |  | 			device_type = "network"; | 
					
						
							|  |  |  | 			model = "TSEC"; | 
					
						
							|  |  |  | 			compatible = "gianfar"; | 
					
						
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										 |  |  | 			reg = <0x24000 0x1000>; | 
					
						
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										 |  |  | 			local-mac-address = [ 00 00 00 00 00 00 ]; | 
					
						
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										 |  |  | 			interrupts = <29 2 30 2 34 2>; | 
					
						
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										 |  |  | 			interrupt-parent = <&mpic>; | 
					
						
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											2008-12-16 15:29:15 -08:00
										 |  |  | 			tbi-handle = <&tbi0>; | 
					
						
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										 |  |  | 			phy-handle = <&phy0>; | 
					
						
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										 |  |  | 		}; | 
					
						
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 | 
					
						
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										 |  |  | 		enet1: ethernet@25000 { | 
					
						
							|  |  |  | 			cell-index = <1>; | 
					
						
							| 
									
										
										
										
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										 |  |  | 			device_type = "network"; | 
					
						
							|  |  |  | 			model = "TSEC"; | 
					
						
							|  |  |  | 			compatible = "gianfar"; | 
					
						
							| 
									
										
										
										
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										 |  |  | 			reg = <0x25000 0x1000>; | 
					
						
							| 
									
										
										
										
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										 |  |  | 			local-mac-address = [ 00 00 00 00 00 00 ]; | 
					
						
							| 
									
										
										
										
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										 |  |  | 			interrupts = <35 2 36 2 40 2>; | 
					
						
							| 
									
										
										
										
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										 |  |  | 			interrupt-parent = <&mpic>; | 
					
						
							| 
									
										
										
										
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										 |  |  | 			tbi-handle = <&tbi1>; | 
					
						
							| 
									
										
										
										
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										 |  |  | 			phy-handle = <&phy1>; | 
					
						
							| 
									
										
										
										
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										 |  |  | 		}; | 
					
						
							|  |  |  | 
 | 
					
						
							| 
									
										
										
										
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										 |  |  | 		enet2: ethernet@26000 { | 
					
						
							|  |  |  | 			cell-index = <2>; | 
					
						
							| 
									
										
										
										
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										 |  |  | 			device_type = "network"; | 
					
						
							| 
									
										
										
										
											2006-08-21 14:29:28 -05:00
										 |  |  | 			model = "FEC"; | 
					
						
							| 
									
										
										
										
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										 |  |  | 			compatible = "gianfar"; | 
					
						
							| 
									
										
										
										
											2008-04-17 01:28:15 -05:00
										 |  |  | 			reg = <0x26000 0x1000>; | 
					
						
							| 
									
										
										
										
											2007-06-22 14:33:15 -05:00
										 |  |  | 			local-mac-address = [ 00 00 00 00 00 00 ]; | 
					
						
							| 
									
										
										
										
											2008-04-17 01:28:15 -05:00
										 |  |  | 			interrupts = <41 2>; | 
					
						
							| 
									
										
										
										
											2007-02-17 16:04:23 -06:00
										 |  |  | 			interrupt-parent = <&mpic>; | 
					
						
							| 
									
										
										
										
											2008-12-16 15:29:15 -08:00
										 |  |  | 			tbi-handle = <&tbi2>; | 
					
						
							| 
									
										
										
										
											2007-02-17 16:04:23 -06:00
										 |  |  | 			phy-handle = <&phy3>; | 
					
						
							| 
									
										
										
										
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										 |  |  | 		}; | 
					
						
							|  |  |  | 
 | 
					
						
							| 
									
										
										
										
											2007-12-12 01:46:12 -06:00
										 |  |  | 		serial0: serial@4500 { | 
					
						
							|  |  |  | 			cell-index = <0>; | 
					
						
							| 
									
										
										
										
											2006-08-18 18:04:34 -05:00
										 |  |  | 			device_type = "serial"; | 
					
						
							|  |  |  | 			compatible = "ns16550"; | 
					
						
							| 
									
										
										
										
											2008-04-17 01:28:15 -05:00
										 |  |  | 			reg = <0x4500 0x100>; 	// reg base, size | 
					
						
							| 
									
										
										
										
											2006-08-18 18:04:34 -05:00
										 |  |  | 			clock-frequency = <0>; 	// should we fill in in uboot? | 
					
						
							| 
									
										
										
										
											2008-04-17 01:28:15 -05:00
										 |  |  | 			interrupts = <42 2>; | 
					
						
							| 
									
										
										
										
											2007-02-17 16:04:23 -06:00
										 |  |  | 			interrupt-parent = <&mpic>; | 
					
						
							| 
									
										
										
										
											2006-08-18 18:04:34 -05:00
										 |  |  | 		}; | 
					
						
							|  |  |  | 
 | 
					
						
							| 
									
										
										
										
											2007-12-12 01:46:12 -06:00
										 |  |  | 		serial1: serial@4600 { | 
					
						
							|  |  |  | 			cell-index = <1>; | 
					
						
							| 
									
										
										
										
											2006-08-18 18:04:34 -05:00
										 |  |  | 			device_type = "serial"; | 
					
						
							|  |  |  | 			compatible = "ns16550"; | 
					
						
							| 
									
										
										
										
											2008-04-17 01:28:15 -05:00
										 |  |  | 			reg = <0x4600 0x100>;	// reg base, size | 
					
						
							| 
									
										
										
										
											2006-08-18 18:04:34 -05:00
										 |  |  | 			clock-frequency = <0>; 	// should we fill in in uboot? | 
					
						
							| 
									
										
										
										
											2008-04-17 01:28:15 -05:00
										 |  |  | 			interrupts = <42 2>; | 
					
						
							| 
									
										
										
										
											2007-02-17 16:04:23 -06:00
										 |  |  | 			interrupt-parent = <&mpic>; | 
					
						
							| 
									
										
										
										
											2006-08-18 18:04:34 -05:00
										 |  |  | 		}; | 
					
						
							| 
									
										
										
										
											2007-09-12 18:23:46 -05:00
										 |  |  | 		mpic: pic@40000 { | 
					
						
							|  |  |  | 			interrupt-controller; | 
					
						
							|  |  |  | 			#address-cells = <0>; | 
					
						
							|  |  |  | 			#interrupt-cells = <2>; | 
					
						
							| 
									
										
										
										
											2008-04-17 01:28:15 -05:00
										 |  |  | 			reg = <0x40000 0x40000>; | 
					
						
							| 
									
										
										
										
											2007-09-12 18:23:46 -05:00
										 |  |  | 			compatible = "chrp,open-pic"; | 
					
						
							|  |  |  | 			device_type = "open-pic"; | 
					
						
							|  |  |  | 		}; | 
					
						
							|  |  |  | 	}; | 
					
						
							| 
									
										
										
										
											2006-08-18 18:04:34 -05:00
										 |  |  | 
 | 
					
						
							| 
									
										
										
										
											2007-12-12 01:46:12 -06:00
										 |  |  | 	pci0: pci@e0008000 { | 
					
						
							|  |  |  | 		cell-index = <0>; | 
					
						
							| 
									
										
										
										
											2008-04-17 01:28:15 -05:00
										 |  |  | 		interrupt-map-mask = <0xf800 0x0 0x0 0x7>; | 
					
						
							| 
									
										
										
										
											2007-09-12 18:23:46 -05:00
										 |  |  | 		interrupt-map = < | 
					
						
							| 
									
										
										
										
											2006-08-18 18:04:34 -05:00
										 |  |  | 
 | 
					
						
							| 
									
										
										
										
											2007-09-12 18:23:46 -05:00
										 |  |  | 			/* IDSEL 0x02 */ | 
					
						
							| 
									
										
										
										
											2008-04-17 01:28:15 -05:00
										 |  |  | 			0x1000 0x0 0x0 0x1 &mpic 0x1 0x1 | 
					
						
							|  |  |  | 			0x1000 0x0 0x0 0x2 &mpic 0x2 0x1 | 
					
						
							|  |  |  | 			0x1000 0x0 0x0 0x3 &mpic 0x3 0x1 | 
					
						
							|  |  |  | 			0x1000 0x0 0x0 0x4 &mpic 0x4 0x1 | 
					
						
							| 
									
										
										
										
											2006-08-18 18:04:34 -05:00
										 |  |  | 
 | 
					
						
							| 
									
										
										
										
											2007-09-12 18:23:46 -05:00
										 |  |  | 			/* IDSEL 0x03 */ | 
					
						
							| 
									
										
										
										
											2008-04-17 01:28:15 -05:00
										 |  |  | 			0x1800 0x0 0x0 0x1 &mpic 0x4 0x1 | 
					
						
							|  |  |  | 			0x1800 0x0 0x0 0x2 &mpic 0x1 0x1 | 
					
						
							|  |  |  | 			0x1800 0x0 0x0 0x3 &mpic 0x2 0x1 | 
					
						
							|  |  |  | 			0x1800 0x0 0x0 0x4 &mpic 0x3 0x1 | 
					
						
							| 
									
										
										
										
											2006-08-18 18:04:34 -05:00
										 |  |  | 
 | 
					
						
							| 
									
										
										
										
											2007-09-12 18:23:46 -05:00
										 |  |  | 			/* IDSEL 0x04 */ | 
					
						
							| 
									
										
										
										
											2008-04-17 01:28:15 -05:00
										 |  |  | 			0x2000 0x0 0x0 0x1 &mpic 0x3 0x1 | 
					
						
							|  |  |  | 			0x2000 0x0 0x0 0x2 &mpic 0x4 0x1 | 
					
						
							|  |  |  | 			0x2000 0x0 0x0 0x3 &mpic 0x1 0x1 | 
					
						
							|  |  |  | 			0x2000 0x0 0x0 0x4 &mpic 0x2 0x1 | 
					
						
							| 
									
										
										
										
											2006-08-18 18:04:34 -05:00
										 |  |  | 
 | 
					
						
							| 
									
										
										
										
											2007-09-12 18:23:46 -05:00
										 |  |  | 			/* IDSEL 0x05 */ | 
					
						
							| 
									
										
										
										
											2008-04-17 01:28:15 -05:00
										 |  |  | 			0x2800 0x0 0x0 0x1 &mpic 0x2 0x1 | 
					
						
							|  |  |  | 			0x2800 0x0 0x0 0x2 &mpic 0x3 0x1 | 
					
						
							|  |  |  | 			0x2800 0x0 0x0 0x3 &mpic 0x4 0x1 | 
					
						
							|  |  |  | 			0x2800 0x0 0x0 0x4 &mpic 0x1 0x1 | 
					
						
							| 
									
										
										
										
											2006-08-18 18:04:34 -05:00
										 |  |  | 
 | 
					
						
							| 
									
										
										
										
											2007-09-12 18:23:46 -05:00
										 |  |  | 			/* IDSEL 0x0c */ | 
					
						
							| 
									
										
										
										
											2008-04-17 01:28:15 -05:00
										 |  |  | 			0x6000 0x0 0x0 0x1 &mpic 0x1 0x1 | 
					
						
							|  |  |  | 			0x6000 0x0 0x0 0x2 &mpic 0x2 0x1 | 
					
						
							|  |  |  | 			0x6000 0x0 0x0 0x3 &mpic 0x3 0x1 | 
					
						
							|  |  |  | 			0x6000 0x0 0x0 0x4 &mpic 0x4 0x1 | 
					
						
							| 
									
										
										
										
											2006-08-18 18:04:34 -05:00
										 |  |  | 
 | 
					
						
							| 
									
										
										
										
											2007-09-12 18:23:46 -05:00
										 |  |  | 			/* IDSEL 0x0d */ | 
					
						
							| 
									
										
										
										
											2008-04-17 01:28:15 -05:00
										 |  |  | 			0x6800 0x0 0x0 0x1 &mpic 0x4 0x1 | 
					
						
							|  |  |  | 			0x6800 0x0 0x0 0x2 &mpic 0x1 0x1 | 
					
						
							|  |  |  | 			0x6800 0x0 0x0 0x3 &mpic 0x2 0x1 | 
					
						
							|  |  |  | 			0x6800 0x0 0x0 0x4 &mpic 0x3 0x1 | 
					
						
							| 
									
										
										
										
											2006-08-18 18:04:34 -05:00
										 |  |  | 
 | 
					
						
							| 
									
										
										
										
											2007-09-12 18:23:46 -05:00
										 |  |  | 			/* IDSEL 0x0e */ | 
					
						
							| 
									
										
										
										
											2008-04-17 01:28:15 -05:00
										 |  |  | 			0x7000 0x0 0x0 0x1 &mpic 0x3 0x1 | 
					
						
							|  |  |  | 			0x7000 0x0 0x0 0x2 &mpic 0x4 0x1 | 
					
						
							|  |  |  | 			0x7000 0x0 0x0 0x3 &mpic 0x1 0x1 | 
					
						
							|  |  |  | 			0x7000 0x0 0x0 0x4 &mpic 0x2 0x1 | 
					
						
							| 
									
										
										
										
											2006-08-18 18:04:34 -05:00
										 |  |  | 
 | 
					
						
							| 
									
										
										
										
											2007-09-12 18:23:46 -05:00
										 |  |  | 			/* IDSEL 0x0f */ | 
					
						
							| 
									
										
										
										
											2008-04-17 01:28:15 -05:00
										 |  |  | 			0x7800 0x0 0x0 0x1 &mpic 0x2 0x1 | 
					
						
							|  |  |  | 			0x7800 0x0 0x0 0x2 &mpic 0x3 0x1 | 
					
						
							|  |  |  | 			0x7800 0x0 0x0 0x3 &mpic 0x4 0x1 | 
					
						
							|  |  |  | 			0x7800 0x0 0x0 0x4 &mpic 0x1 0x1 | 
					
						
							| 
									
										
										
										
											2006-08-18 18:04:34 -05:00
										 |  |  | 
 | 
					
						
							| 
									
										
										
										
											2007-09-12 18:23:46 -05:00
										 |  |  | 			/* IDSEL 0x12 */ | 
					
						
							| 
									
										
										
										
											2008-04-17 01:28:15 -05:00
										 |  |  | 			0x9000 0x0 0x0 0x1 &mpic 0x1 0x1 | 
					
						
							|  |  |  | 			0x9000 0x0 0x0 0x2 &mpic 0x2 0x1 | 
					
						
							|  |  |  | 			0x9000 0x0 0x0 0x3 &mpic 0x3 0x1 | 
					
						
							|  |  |  | 			0x9000 0x0 0x0 0x4 &mpic 0x4 0x1 | 
					
						
							| 
									
										
										
										
											2006-08-18 18:04:34 -05:00
										 |  |  | 
 | 
					
						
							| 
									
										
										
										
											2007-09-12 18:23:46 -05:00
										 |  |  | 			/* IDSEL 0x13 */ | 
					
						
							| 
									
										
										
										
											2008-04-17 01:28:15 -05:00
										 |  |  | 			0x9800 0x0 0x0 0x1 &mpic 0x4 0x1 | 
					
						
							|  |  |  | 			0x9800 0x0 0x0 0x2 &mpic 0x1 0x1 | 
					
						
							|  |  |  | 			0x9800 0x0 0x0 0x3 &mpic 0x2 0x1 | 
					
						
							|  |  |  | 			0x9800 0x0 0x0 0x4 &mpic 0x3 0x1 | 
					
						
							| 
									
										
										
										
											2006-08-18 18:04:34 -05:00
										 |  |  | 
 | 
					
						
							| 
									
										
										
										
											2007-09-12 18:23:46 -05:00
										 |  |  | 			/* IDSEL 0x14 */ | 
					
						
							| 
									
										
										
										
											2008-04-17 01:28:15 -05:00
										 |  |  | 			0xa000 0x0 0x0 0x1 &mpic 0x3 0x1 | 
					
						
							|  |  |  | 			0xa000 0x0 0x0 0x2 &mpic 0x4 0x1 | 
					
						
							|  |  |  | 			0xa000 0x0 0x0 0x3 &mpic 0x1 0x1 | 
					
						
							|  |  |  | 			0xa000 0x0 0x0 0x4 &mpic 0x2 0x1 | 
					
						
							| 
									
										
										
										
											2006-08-18 18:04:34 -05:00
										 |  |  | 
 | 
					
						
							| 
									
										
										
										
											2007-09-12 18:23:46 -05:00
										 |  |  | 			/* IDSEL 0x15 */ | 
					
						
							| 
									
										
										
										
											2008-04-17 01:28:15 -05:00
										 |  |  | 			0xa800 0x0 0x0 0x1 &mpic 0x2 0x1 | 
					
						
							|  |  |  | 			0xa800 0x0 0x0 0x2 &mpic 0x3 0x1 | 
					
						
							|  |  |  | 			0xa800 0x0 0x0 0x3 &mpic 0x4 0x1 | 
					
						
							|  |  |  | 			0xa800 0x0 0x0 0x4 &mpic 0x1 0x1>; | 
					
						
							| 
									
										
										
										
											2007-09-12 18:23:46 -05:00
										 |  |  | 		interrupt-parent = <&mpic>; | 
					
						
							| 
									
										
										
										
											2008-04-17 01:28:15 -05:00
										 |  |  | 		interrupts = <24 2>; | 
					
						
							| 
									
										
										
										
											2007-09-12 18:23:46 -05:00
										 |  |  | 		bus-range = <0 0>; | 
					
						
							| 
									
										
										
										
											2008-04-17 01:28:15 -05:00
										 |  |  | 		ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000 | 
					
						
							|  |  |  | 			  0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>; | 
					
						
							|  |  |  | 		clock-frequency = <66666666>; | 
					
						
							| 
									
										
										
										
											2007-09-12 18:23:46 -05:00
										 |  |  | 		#interrupt-cells = <1>; | 
					
						
							|  |  |  | 		#size-cells = <2>; | 
					
						
							|  |  |  | 		#address-cells = <3>; | 
					
						
							| 
									
										
										
										
											2008-04-17 01:28:15 -05:00
										 |  |  | 		reg = <0xe0008000 0x1000>; | 
					
						
							| 
									
										
										
										
											2007-09-12 18:23:46 -05:00
										 |  |  | 		compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; | 
					
						
							|  |  |  | 		device_type = "pci"; | 
					
						
							| 
									
										
										
										
											2006-08-18 18:04:34 -05:00
										 |  |  | 	}; | 
					
						
							|  |  |  | }; |