88 lines
3 KiB
C
88 lines
3 KiB
C
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/* linux/arch/arm/plat-s3c/include/plat/regs-sdhci.h
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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* http://armlinux.simtec.co.uk/
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* Ben Dooks <ben@simtec.co.uk>
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*
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* S3C Platform - SDHCI (HSMMC) register definitions
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __PLAT_S3C_SDHCI_REGS_H
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#define __PLAT_S3C_SDHCI_REGS_H __FILE__
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#define S3C_SDHCI_CONTROL2 (0x80)
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#define S3C_SDHCI_CONTROL3 (0x84)
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#define S3C64XX_SDHCI_CONTROL4 (0x8C)
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#define S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR (1 << 31)
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#define S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK (1 << 30)
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#define S3C_SDHCI_CTRL2_CDINVRXD3 (1 << 29)
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#define S3C_SDHCI_CTRL2_SLCARDOUT (1 << 28)
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#define S3C_SDHCI_CTRL2_FLTCLKSEL_MASK (0xf << 24)
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#define S3C_SDHCI_CTRL2_FLTCLKSEL_SHIFT (24)
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#define S3C_SDHCI_CTRL2_FLTCLKSEL(_x) ((_x) << 24)
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#define S3C_SDHCI_CTRL2_LVLDAT_MASK (0xff << 16)
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#define S3C_SDHCI_CTRL2_LVLDAT_SHIFT (16)
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#define S3C_SDHCI_CTRL2_LVLDAT(_x) ((_x) << 16)
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#define S3C_SDHCI_CTRL2_ENFBCLKTX (1 << 15)
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#define S3C_SDHCI_CTRL2_ENFBCLKRX (1 << 14)
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#define S3C_SDHCI_CTRL2_SDCDSEL (1 << 13)
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#define S3C_SDHCI_CTRL2_SDSIGPC (1 << 12)
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#define S3C_SDHCI_CTRL2_ENBUSYCHKTXSTART (1 << 11)
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#define S3C_SDHCI_CTRL2_DFCNT_MASK (0x3 << 9)
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#define S3C_SDHCI_CTRL2_DFCNT_SHIFT (9)
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#define S3C_SDHCI_CTRL2_DFCNT_NONE (0x0 << 9)
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#define S3C_SDHCI_CTRL2_DFCNT_4SDCLK (0x1 << 9)
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#define S3C_SDHCI_CTRL2_DFCNT_16SDCLK (0x2 << 9)
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#define S3C_SDHCI_CTRL2_DFCNT_64SDCLK (0x3 << 9)
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#define S3C_SDHCI_CTRL2_ENCLKOUTHOLD (1 << 8)
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#define S3C_SDHCI_CTRL2_RWAITMODE (1 << 7)
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#define S3C_SDHCI_CTRL2_DISBUFRD (1 << 6)
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#define S3C_SDHCI_CTRL2_SELBASECLK_MASK (0x3 << 4)
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#define S3C_SDHCI_CTRL2_SELBASECLK_SHIFT (4)
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#define S3C_SDHCI_CTRL2_PWRSYNC (1 << 3)
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#define S3C_SDHCI_CTRL2_ENCLKOUTMSKCON (1 << 1)
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#define S3C_SDHCI_CTRL2_HWINITFIN (1 << 0)
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#define S3C_SDHCI_CTRL3_FCSEL3 (1 << 31)
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#define S3C_SDHCI_CTRL3_FCSEL2 (1 << 23)
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#define S3C_SDHCI_CTRL3_FCSEL1 (1 << 15)
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#define S3C_SDHCI_CTRL3_FCSEL0 (1 << 7)
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#define S3C_SDHCI_CTRL3_FIA3_MASK (0x7f << 24)
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#define S3C_SDHCI_CTRL3_FIA3_SHIFT (24)
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#define S3C_SDHCI_CTRL3_FIA3(_x) ((_x) << 24)
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#define S3C_SDHCI_CTRL3_FIA2_MASK (0x7f << 16)
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#define S3C_SDHCI_CTRL3_FIA2_SHIFT (16)
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#define S3C_SDHCI_CTRL3_FIA2(_x) ((_x) << 16)
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#define S3C_SDHCI_CTRL3_FIA1_MASK (0x7f << 8)
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#define S3C_SDHCI_CTRL3_FIA1_SHIFT (8)
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#define S3C_SDHCI_CTRL3_FIA1(_x) ((_x) << 8)
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#define S3C_SDHCI_CTRL3_FIA0_MASK (0x7f << 0)
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#define S3C_SDHCI_CTRL3_FIA0_SHIFT (0)
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#define S3C_SDHCI_CTRL3_FIA0(_x) ((_x) << 0)
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#define S3C64XX_SDHCI_CONTROL4_DRIVE_MASK (0x3 << 16)
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#define S3C64XX_SDHCI_CONTROL4_DRIVE_SHIFT (16)
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#define S3C64XX_SDHCI_CONTROL4_DRIVE_2mA (0x0 << 16)
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#define S3C64XX_SDHCI_CONTROL4_DRIVE_4mA (0x1 << 16)
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#define S3C64XX_SDHCI_CONTROL4_DRIVE_7mA (0x2 << 16)
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#define S3C64XX_SDHCI_CONTROL4_DRIVE_9mA (0x3 << 16)
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#define S3C64XX_SDHCI_CONTROL4_BUSY (1)
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#endif /* __PLAT_S3C_SDHCI_REGS_H */
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