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										 |  |  | /*******************************************************************************
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							|  |  |  |   Intel 10 Gigabit PCI Express Linux driver | 
					
						
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											2010-01-13 01:49:34 +00:00
										 |  |  |   Copyright(c) 1999 - 2010 Intel Corporation. | 
					
						
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							|  |  |  |   This program is free software; you can redistribute it and/or modify it | 
					
						
							|  |  |  |   under the terms and conditions of the GNU General Public License, | 
					
						
							|  |  |  |   version 2, as published by the Free Software Foundation. | 
					
						
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							|  |  |  |   This program is distributed in the hope it will be useful, but WITHOUT | 
					
						
							|  |  |  |   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | 
					
						
							|  |  |  |   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for | 
					
						
							|  |  |  |   more details. | 
					
						
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							|  |  |  |   You should have received a copy of the GNU General Public License along with | 
					
						
							|  |  |  |   this program; if not, write to the Free Software Foundation, Inc., | 
					
						
							|  |  |  |   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | 
					
						
							|  |  |  | 
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							|  |  |  |   The full GNU General Public License is included in this distribution in | 
					
						
							|  |  |  |   the file called "COPYING". | 
					
						
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							|  |  |  |   Contact Information: | 
					
						
							|  |  |  |   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | 
					
						
							|  |  |  |   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | 
					
						
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							|  |  |  | *******************************************************************************/ | 
					
						
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							|  |  |  | #ifndef _IXGBE_PHY_H_
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							|  |  |  | #define _IXGBE_PHY_H_
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							|  |  |  | #include "ixgbe_type.h"
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										 |  |  | #define IXGBE_I2C_EEPROM_DEV_ADDR    0xA0
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										 |  |  | /* EEPROM byte offsets */ | 
					
						
							|  |  |  | #define IXGBE_SFF_IDENTIFIER         0x0
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							|  |  |  | #define IXGBE_SFF_IDENTIFIER_SFP     0x3
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							|  |  |  | #define IXGBE_SFF_VENDOR_OUI_BYTE0   0x25
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							|  |  |  | #define IXGBE_SFF_VENDOR_OUI_BYTE1   0x26
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							|  |  |  | #define IXGBE_SFF_VENDOR_OUI_BYTE2   0x27
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							|  |  |  | #define IXGBE_SFF_1GBE_COMP_CODES    0x6
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							|  |  |  | #define IXGBE_SFF_10GBE_COMP_CODES   0x3
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										 |  |  | #define IXGBE_SFF_CABLE_TECHNOLOGY   0x8
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										 |  |  | #define IXGBE_SFF_CABLE_SPEC_COMP    0x3C
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							|  |  |  | /* Bitmasks */ | 
					
						
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										 |  |  | #define IXGBE_SFF_DA_PASSIVE_CABLE           0x4
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										 |  |  | #define IXGBE_SFF_DA_ACTIVE_CABLE            0x8
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							|  |  |  | #define IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING    0x4
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										 |  |  | #define IXGBE_SFF_1GBASESX_CAPABLE           0x1
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										 |  |  | #define IXGBE_SFF_1GBASELX_CAPABLE           0x2
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										 |  |  | #define IXGBE_SFF_1GBASET_CAPABLE            0x8
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										 |  |  | #define IXGBE_SFF_10GBASESR_CAPABLE          0x10
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							|  |  |  | #define IXGBE_SFF_10GBASELR_CAPABLE          0x20
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							|  |  |  | #define IXGBE_I2C_EEPROM_READ_MASK           0x100
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							|  |  |  | #define IXGBE_I2C_EEPROM_STATUS_MASK         0x3
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							|  |  |  | #define IXGBE_I2C_EEPROM_STATUS_NO_OPERATION 0x0
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							|  |  |  | #define IXGBE_I2C_EEPROM_STATUS_PASS         0x1
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							|  |  |  | #define IXGBE_I2C_EEPROM_STATUS_FAIL         0x2
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							|  |  |  | #define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS  0x3
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							|  |  |  | /* Bit-shift macros */ | 
					
						
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										 |  |  | #define IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT    24
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							|  |  |  | #define IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT    16
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							|  |  |  | #define IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT    8
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							|  |  |  | /* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */ | 
					
						
							|  |  |  | #define IXGBE_SFF_VENDOR_OUI_TYCO     0x00407600
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							|  |  |  | #define IXGBE_SFF_VENDOR_OUI_FTL      0x00906500
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							|  |  |  | #define IXGBE_SFF_VENDOR_OUI_AVAGO    0x00176A00
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										 |  |  | #define IXGBE_SFF_VENDOR_OUI_INTEL    0x001B2100
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										 |  |  | /* I2C SDA and SCL timing parameters for standard mode */ | 
					
						
							|  |  |  | #define IXGBE_I2C_T_HD_STA  4
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							|  |  |  | #define IXGBE_I2C_T_LOW     5
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							|  |  |  | #define IXGBE_I2C_T_HIGH    4
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							|  |  |  | #define IXGBE_I2C_T_SU_STA  5
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							|  |  |  | #define IXGBE_I2C_T_HD_DATA 5
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							|  |  |  | #define IXGBE_I2C_T_SU_DATA 1
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							|  |  |  | #define IXGBE_I2C_T_RISE    1
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							|  |  |  | #define IXGBE_I2C_T_FALL    1
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							|  |  |  | #define IXGBE_I2C_T_SU_STO  4
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							|  |  |  | #define IXGBE_I2C_T_BUF     5
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										 |  |  | #define IXGBE_TN_LASI_STATUS_REG        0x9005
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							|  |  |  | #define IXGBE_TN_LASI_STATUS_TEMP_ALARM 0x0008
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							|  |  |  | s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw); | 
					
						
							|  |  |  | s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw); | 
					
						
							|  |  |  | s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw); | 
					
						
							|  |  |  | s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, | 
					
						
							|  |  |  |                                u32 device_type, u16 *phy_data); | 
					
						
							|  |  |  | s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, | 
					
						
							|  |  |  |                                 u32 device_type, u16 phy_data); | 
					
						
							|  |  |  | s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw); | 
					
						
							|  |  |  | s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, | 
					
						
							|  |  |  |                                        ixgbe_link_speed speed, | 
					
						
							|  |  |  |                                        bool autoneg, | 
					
						
							|  |  |  |                                        bool autoneg_wait_to_complete); | 
					
						
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										 |  |  | /* PHY specific */ | 
					
						
							|  |  |  | s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, | 
					
						
							|  |  |  |                              ixgbe_link_speed *speed, | 
					
						
							|  |  |  |                              bool *link_up); | 
					
						
							|  |  |  | s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, | 
					
						
							|  |  |  |                                        u16 *firmware_version); | 
					
						
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										 |  |  | s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw); | 
					
						
							|  |  |  | s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw); | 
					
						
							|  |  |  | s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, | 
					
						
							|  |  |  |                                         u16 *list_offset, | 
					
						
							|  |  |  |                                         u16 *data_offset); | 
					
						
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										 |  |  | s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw); | 
					
						
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										 |  |  | s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, | 
					
						
							|  |  |  |                                 u8 dev_addr, u8 *data); | 
					
						
							|  |  |  | s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, | 
					
						
							|  |  |  |                                  u8 dev_addr, u8 data); | 
					
						
							|  |  |  | s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, | 
					
						
							|  |  |  |                                   u8 *eeprom_data); | 
					
						
							|  |  |  | s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, | 
					
						
							|  |  |  |                                    u8 eeprom_data); | 
					
						
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										 |  |  | #endif /* _IXGBE_PHY_H_ */
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