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										 |  |  | /* $Id: boardergo.h,v 1.2.6.1 2001/09/23 22:24:54 kai Exp $
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							|  |  |  |  * | 
					
						
							|  |  |  |  * Linux driver for HYSDN cards, definitions for ergo type boards (buffers..). | 
					
						
							|  |  |  |  * | 
					
						
							|  |  |  |  * Author    Werner Cornelius (werner@titro.de) for Hypercope GmbH | 
					
						
							|  |  |  |  * Copyright 1999 by Werner Cornelius (werner@titro.de) | 
					
						
							|  |  |  |  * | 
					
						
							|  |  |  |  * This software may be used and distributed according to the terms | 
					
						
							|  |  |  |  * of the GNU General Public License, incorporated herein by reference. | 
					
						
							|  |  |  |  * | 
					
						
							|  |  |  |  */ | 
					
						
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							|  |  |  | /************************************************/ | 
					
						
							|  |  |  | /* defines for the dual port memory of the card */ | 
					
						
							|  |  |  | /************************************************/ | 
					
						
							|  |  |  | #define ERG_DPRAM_PAGE_SIZE 0x2000	/* DPRAM occupies a 8K page */
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							|  |  |  | #define BOOT_IMG_SIZE 4096
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							|  |  |  | #define ERG_DPRAM_FILL_SIZE (ERG_DPRAM_PAGE_SIZE - BOOT_IMG_SIZE)
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							|  |  |  | #define ERG_TO_HY_BUF_SIZE  0x0E00	/* 3072 bytes buffer size to card */
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							|  |  |  | #define ERG_TO_PC_BUF_SIZE  0x0E00	/* 3072 bytes to PC, too */
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							|  |  |  | /* following DPRAM layout copied from OS2-driver boarderg.h */ | 
					
						
							|  |  |  | typedef struct ErgDpram_tag { | 
					
						
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										 |  |  | /*0000 */ unsigned char ToHyBuf[ERG_TO_HY_BUF_SIZE]; | 
					
						
							|  |  |  | /*0E00 */ unsigned char ToPcBuf[ERG_TO_PC_BUF_SIZE]; | 
					
						
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										 |  |  | 	/*1C00 */ unsigned char bSoftUart[SIZE_RSV_SOFT_UART]; | 
					
						
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										 |  |  | 	/* size 0x1B0 */ | 
					
						
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										 |  |  | 	/*1DB0 *//* tErrLogEntry */ unsigned char volatile ErrLogMsg[64]; | 
					
						
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										 |  |  | 	/* size 64 bytes */ | 
					
						
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										 |  |  | 	/*1DB0  unsigned long ulErrType;               */ | 
					
						
							|  |  |  | 	/*1DB4  unsigned long ulErrSubtype;            */ | 
					
						
							|  |  |  | 	/*1DB8  unsigned long ucTextSize;              */ | 
					
						
							|  |  |  | 	/*1DB9  unsigned long ucText[ERRLOG_TEXT_SIZE]; *//* ASCIIZ of len ucTextSize-1 */ | 
					
						
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										 |  |  | 	/*1DF0 */ | 
					
						
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										 |  |  | /*1DF0 */ unsigned short volatile ToHyChannel; | 
					
						
							|  |  |  | /*1DF2 */ unsigned short volatile ToHySize; | 
					
						
							|  |  |  | 	/*1DF4 */ unsigned char volatile ToHyFlag; | 
					
						
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										 |  |  | 	/* !=0: msg for Hy waiting */ | 
					
						
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										 |  |  | 	/*1DF5 */ unsigned char volatile ToPcFlag; | 
					
						
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										 |  |  | 	/* !=0: msg for PC waiting */ | 
					
						
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										 |  |  | /*1DF6 */ unsigned short volatile ToPcChannel; | 
					
						
							|  |  |  | /*1DF8 */ unsigned short volatile ToPcSize; | 
					
						
							|  |  |  | 	/*1DFA */ unsigned char bRes1DBA[0x1E00 - 0x1DFA]; | 
					
						
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										 |  |  | 	/* 6 bytes */ | 
					
						
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										 |  |  | /*1E00 */ unsigned char bRestOfEntryTbl[0x1F00 - 0x1E00]; | 
					
						
							|  |  |  | /*1F00 */ unsigned long TrapTable[62]; | 
					
						
							|  |  |  | 	/*1FF8 */ unsigned char bRes1FF8[0x1FFB - 0x1FF8]; | 
					
						
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										 |  |  | 	/* low part of reset vetor */ | 
					
						
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										 |  |  | /*1FFB */ unsigned char ToPcIntMetro; | 
					
						
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										 |  |  | 	/* notes:
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							|  |  |  | 	 * - metro has 32-bit boot ram - accessing | 
					
						
							|  |  |  | 	 *   ToPcInt and ToHyInt would be the same; | 
					
						
							|  |  |  | 	 *   so we moved ToPcInt to 1FFB. | 
					
						
							|  |  |  | 	 *   Because on the PC side both vars are | 
					
						
							|  |  |  | 	 *   readonly (reseting on int from E1 to PC), | 
					
						
							|  |  |  | 	 *   we can read both vars on both cards | 
					
						
							|  |  |  | 	 *   without destroying anything. | 
					
						
							|  |  |  | 	 * - 1FFB is the high byte of the reset vector, | 
					
						
							|  |  |  | 	 *   so E1 side should NOT change this byte | 
					
						
							|  |  |  | 	 *   when writing! | 
					
						
							|  |  |  | 	 */ | 
					
						
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										 |  |  | /*1FFC */ unsigned char volatile ToHyNoDpramErrLog; | 
					
						
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										 |  |  | 	/* note: ToHyNoDpramErrLog is used to inform
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							|  |  |  | 	 *       boot loader, not to use DPRAM based | 
					
						
							|  |  |  | 	 *       ErrLog; when DOS driver is rewritten | 
					
						
							|  |  |  | 	 *       this becomes obsolete | 
					
						
							|  |  |  | 	 */ | 
					
						
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										 |  |  | /*1FFD */ unsigned char bRes1FFD; | 
					
						
							|  |  |  | 	/*1FFE */ unsigned char ToPcInt; | 
					
						
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										 |  |  | 	/* E1_intclear; on CHAMP2: E1_intset   */ | 
					
						
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										 |  |  | 	/*1FFF */ unsigned char ToHyInt; | 
					
						
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										 |  |  | 	/* E1_intset;   on CHAMP2: E1_intclear */ | 
					
						
							|  |  |  | } tErgDpram; | 
					
						
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							|  |  |  | /**********************************************/ | 
					
						
							|  |  |  | /* PCI9050 controller local register offsets: */ | 
					
						
							|  |  |  | /* copied from boarderg.c                     */ | 
					
						
							|  |  |  | /**********************************************/ | 
					
						
							|  |  |  | #define PCI9050_INTR_REG    0x4C	/* Interrupt register */
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							|  |  |  | #define PCI9050_USER_IO     0x51	/* User I/O  register */
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							|  |  |  | 				    /* bitmask for PCI9050_INTR_REG: */ | 
					
						
							|  |  |  | #define PCI9050_INTR_REG_EN1    0x01	/* 1= enable (def.), 0= disable */
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							|  |  |  | #define PCI9050_INTR_REG_POL1   0x02	/* 1= active high (def.), 0= active low */
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							|  |  |  | #define PCI9050_INTR_REG_STAT1  0x04	/* 1= intr. active, 0= intr. not active (def.) */
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							|  |  |  | #define PCI9050_INTR_REG_ENPCI  0x40	/* 1= PCI interrupts enable (def.) */
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							|  |  |  | 				    /* bitmask for PCI9050_USER_IO: */ | 
					
						
							|  |  |  | #define PCI9050_USER_IO_EN3     0x02	/* 1= disable      , 0= enable (def.) */
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							|  |  |  | #define PCI9050_USER_IO_DIR3    0x04	/* 1= output (def.), 0= input         */
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							|  |  |  | #define PCI9050_USER_IO_DAT3    0x08	/* 1= high (def.)  , 0= low           */
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							|  |  |  | #define PCI9050_E1_RESET    (                     PCI9050_USER_IO_DIR3)		/* 0x04 */
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							|  |  |  | #define PCI9050_E1_RUN      (PCI9050_USER_IO_DAT3|PCI9050_USER_IO_DIR3)		/* 0x0C */
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