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										 |  |  | #ifndef _CAN_PLATFORM_SJA1000_H
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							|  |  |  | #define _CAN_PLATFORM_SJA1000_H
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							|  |  |  | /* clock divider register */ | 
					
						
							|  |  |  | #define CDR_CLKOUT_MASK 0x07
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							|  |  |  | #define CDR_CLK_OFF	0x08 /* Clock off (CLKOUT pin) */
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							|  |  |  | #define CDR_RXINPEN	0x20 /* TX1 output is RX irq output */
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							|  |  |  | #define CDR_CBP		0x40 /* CAN input comparator bypass */
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							|  |  |  | #define CDR_PELICAN	0x80 /* PeliCAN mode */
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							|  |  |  | /* output control register */ | 
					
						
							|  |  |  | #define OCR_MODE_BIPHASE  0x00
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							|  |  |  | #define OCR_MODE_TEST     0x01
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							|  |  |  | #define OCR_MODE_NORMAL   0x02
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							|  |  |  | #define OCR_MODE_CLOCK    0x03
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										 |  |  | #define OCR_MODE_MASK     0x07
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										 |  |  | #define OCR_TX0_INVERT    0x04
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							|  |  |  | #define OCR_TX0_PULLDOWN  0x08
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							|  |  |  | #define OCR_TX0_PULLUP    0x10
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							|  |  |  | #define OCR_TX0_PUSHPULL  0x18
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							|  |  |  | #define OCR_TX1_INVERT    0x20
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							|  |  |  | #define OCR_TX1_PULLDOWN  0x40
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							|  |  |  | #define OCR_TX1_PULLUP    0x80
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							|  |  |  | #define OCR_TX1_PUSHPULL  0xc0
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										 |  |  | #define OCR_TX_MASK       0xfc
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							|  |  |  | #define OCR_TX_SHIFT      2
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							|  |  |  | struct sja1000_platform_data { | 
					
						
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										 |  |  | 	u32 osc_freq;	/* CAN bus oscillator frequency in Hz */ | 
					
						
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							|  |  |  | 	u8 ocr;		/* output control register */ | 
					
						
							|  |  |  | 	u8 cdr;		/* clock divider register */ | 
					
						
							|  |  |  | }; | 
					
						
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										 |  |  | #endif	/* !_CAN_PLATFORM_SJA1000_H */
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