drm/msm: add mdp5/apq8x74
Add support for the new MDP5 display controller block. The mapping
between parts of the display controller and KMS is:
plane -> PIPE{RGBn,VIGn} \
crtc -> LM (layer mixer) |-> MDP "device"
encoder -> INTF /
connector -> HDMI/DSI/eDP/etc --> other device(s)
Unlike MDP4, it appears we can get by with a single encoder, rather
than needing a different implementation for DTV, DSI, etc. (Ie. the
register interface is same, just different bases.)
Also unlike MDP4, all the IRQs for other blocks (HDMI, DSI, etc) are
routed through MDP.
And finally, MDP5 has this "Shared Memory Pool" (called "SMP"), from
which blocks need to be allocated to the active pipes based on fetch
stride.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-11-30 17:51:47 -05:00
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/*
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* Copyright (C) 2013 Red Hat
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* Author: Rob Clark <robdclark@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "mdp5_kms.h"
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struct mdp5_plane {
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struct drm_plane base;
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const char *name;
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enum mdp5_pipe pipe;
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uint32_t nformats;
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uint32_t formats[32];
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bool enabled;
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};
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#define to_mdp5_plane(x) container_of(x, struct mdp5_plane, base)
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static struct mdp5_kms *get_kms(struct drm_plane *plane)
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{
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struct msm_drm_private *priv = plane->dev->dev_private;
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return to_mdp5_kms(to_mdp_kms(priv->kms));
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}
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static int mdp5_plane_update(struct drm_plane *plane,
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struct drm_crtc *crtc, struct drm_framebuffer *fb,
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int crtc_x, int crtc_y,
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unsigned int crtc_w, unsigned int crtc_h,
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uint32_t src_x, uint32_t src_y,
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uint32_t src_w, uint32_t src_h)
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{
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struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
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mdp5_plane->enabled = true;
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if (plane->fb)
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drm_framebuffer_unreference(plane->fb);
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drm_framebuffer_reference(fb);
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return mdp5_plane_mode_set(plane, crtc, fb,
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crtc_x, crtc_y, crtc_w, crtc_h,
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src_x, src_y, src_w, src_h);
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}
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static int mdp5_plane_disable(struct drm_plane *plane)
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{
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struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
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struct mdp5_kms *mdp5_kms = get_kms(plane);
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enum mdp5_pipe pipe = mdp5_plane->pipe;
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int i;
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DBG("%s: disable", mdp5_plane->name);
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/* update our SMP request to zero (release all our blks): */
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for (i = 0; i < pipe2nclients(pipe); i++)
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mdp5_smp_request(mdp5_kms, pipe2client(pipe, i), 0);
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/* TODO detaching now will cause us not to get the last
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* vblank and mdp5_smp_commit().. so other planes will
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* still see smp blocks previously allocated to us as
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* in-use..
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*/
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if (plane->crtc)
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mdp5_crtc_detach(plane->crtc, plane);
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return 0;
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}
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static void mdp5_plane_destroy(struct drm_plane *plane)
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{
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struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
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2014-04-25 12:30:53 -04:00
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struct msm_drm_private *priv = plane->dev->dev_private;
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if (priv->kms)
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mdp5_plane_disable(plane);
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drm/msm: add mdp5/apq8x74
Add support for the new MDP5 display controller block. The mapping
between parts of the display controller and KMS is:
plane -> PIPE{RGBn,VIGn} \
crtc -> LM (layer mixer) |-> MDP "device"
encoder -> INTF /
connector -> HDMI/DSI/eDP/etc --> other device(s)
Unlike MDP4, it appears we can get by with a single encoder, rather
than needing a different implementation for DTV, DSI, etc. (Ie. the
register interface is same, just different bases.)
Also unlike MDP4, all the IRQs for other blocks (HDMI, DSI, etc) are
routed through MDP.
And finally, MDP5 has this "Shared Memory Pool" (called "SMP"), from
which blocks need to be allocated to the active pipes based on fetch
stride.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-11-30 17:51:47 -05:00
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drm_plane_cleanup(plane);
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kfree(mdp5_plane);
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}
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/* helper to install properties which are common to planes and crtcs */
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void mdp5_plane_install_properties(struct drm_plane *plane,
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struct drm_mode_object *obj)
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{
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// XXX
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}
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int mdp5_plane_set_property(struct drm_plane *plane,
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struct drm_property *property, uint64_t val)
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{
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// XXX
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return -EINVAL;
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}
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static const struct drm_plane_funcs mdp5_plane_funcs = {
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.update_plane = mdp5_plane_update,
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.disable_plane = mdp5_plane_disable,
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.destroy = mdp5_plane_destroy,
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.set_property = mdp5_plane_set_property,
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};
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void mdp5_plane_set_scanout(struct drm_plane *plane,
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struct drm_framebuffer *fb)
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{
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struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
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struct mdp5_kms *mdp5_kms = get_kms(plane);
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enum mdp5_pipe pipe = mdp5_plane->pipe;
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uint32_t nplanes = drm_format_num_planes(fb->pixel_format);
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uint32_t iova[4];
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int i;
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for (i = 0; i < nplanes; i++) {
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struct drm_gem_object *bo = msm_framebuffer_bo(fb, i);
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msm_gem_get_iova(bo, mdp5_kms->id, &iova[i]);
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}
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for (; i < 4; i++)
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iova[i] = 0;
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mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_A(pipe),
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MDP5_PIPE_SRC_STRIDE_A_P0(fb->pitches[0]) |
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MDP5_PIPE_SRC_STRIDE_A_P1(fb->pitches[1]));
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mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_B(pipe),
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MDP5_PIPE_SRC_STRIDE_B_P2(fb->pitches[2]) |
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MDP5_PIPE_SRC_STRIDE_B_P3(fb->pitches[3]));
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mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC0_ADDR(pipe), iova[0]);
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mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC1_ADDR(pipe), iova[1]);
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mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC2_ADDR(pipe), iova[2]);
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mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC3_ADDR(pipe), iova[3]);
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plane->fb = fb;
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}
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/* NOTE: looks like if horizontal decimation is used (if we supported that)
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* then the width used to calculate SMP block requirements is the post-
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* decimated width. Ie. SMP buffering sits downstream of decimation (which
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* presumably happens during the dma from scanout buffer).
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*/
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static int request_smp_blocks(struct drm_plane *plane, uint32_t format,
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uint32_t nplanes, uint32_t width)
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{
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struct drm_device *dev = plane->dev;
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struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
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struct mdp5_kms *mdp5_kms = get_kms(plane);
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enum mdp5_pipe pipe = mdp5_plane->pipe;
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int i, hsub, nlines, nblks, ret;
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hsub = drm_format_horz_chroma_subsampling(format);
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/* different if BWC (compressed framebuffer?) enabled: */
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nlines = 2;
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for (i = 0, nblks = 0; i < nplanes; i++) {
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int n, fetch_stride, cpp;
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cpp = drm_format_plane_cpp(format, i);
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fetch_stride = width * cpp / (i ? hsub : 1);
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n = DIV_ROUND_UP(fetch_stride * nlines, SMP_BLK_SIZE);
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/* for hw rev v1.00 */
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if (mdp5_kms->rev == 0)
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n = roundup_pow_of_two(n);
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DBG("%s[%d]: request %d SMP blocks", mdp5_plane->name, i, n);
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ret = mdp5_smp_request(mdp5_kms, pipe2client(pipe, i), n);
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if (ret) {
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dev_err(dev->dev, "Could not allocate %d SMP blocks: %d\n",
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n, ret);
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return ret;
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}
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nblks += n;
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}
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/* in success case, return total # of blocks allocated: */
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return nblks;
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}
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static void set_fifo_thresholds(struct drm_plane *plane, int nblks)
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{
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struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
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struct mdp5_kms *mdp5_kms = get_kms(plane);
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enum mdp5_pipe pipe = mdp5_plane->pipe;
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uint32_t val;
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/* 1/4 of SMP pool that is being fetched */
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val = (nblks * SMP_ENTRIES_PER_BLK) / 4;
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mdp5_write(mdp5_kms, REG_MDP5_PIPE_REQPRIO_FIFO_WM_0(pipe), val * 1);
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mdp5_write(mdp5_kms, REG_MDP5_PIPE_REQPRIO_FIFO_WM_1(pipe), val * 2);
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mdp5_write(mdp5_kms, REG_MDP5_PIPE_REQPRIO_FIFO_WM_2(pipe), val * 3);
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}
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int mdp5_plane_mode_set(struct drm_plane *plane,
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struct drm_crtc *crtc, struct drm_framebuffer *fb,
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int crtc_x, int crtc_y,
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unsigned int crtc_w, unsigned int crtc_h,
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uint32_t src_x, uint32_t src_y,
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uint32_t src_w, uint32_t src_h)
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{
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struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
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struct mdp5_kms *mdp5_kms = get_kms(plane);
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enum mdp5_pipe pipe = mdp5_plane->pipe;
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const struct mdp_format *format;
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uint32_t nplanes, config = 0;
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uint32_t phasex_step = 0, phasey_step = 0;
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uint32_t hdecm = 0, vdecm = 0;
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int i, nblks;
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nplanes = drm_format_num_planes(fb->pixel_format);
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/* bad formats should already be rejected: */
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if (WARN_ON(nplanes > pipe2nclients(pipe)))
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return -EINVAL;
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/* src values are in Q16 fixed point, convert to integer: */
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src_x = src_x >> 16;
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src_y = src_y >> 16;
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src_w = src_w >> 16;
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src_h = src_h >> 16;
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DBG("%s: FB[%u] %u,%u,%u,%u -> CRTC[%u] %d,%d,%u,%u", mdp5_plane->name,
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fb->base.id, src_x, src_y, src_w, src_h,
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crtc->base.id, crtc_x, crtc_y, crtc_w, crtc_h);
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/*
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* Calculate and request required # of smp blocks:
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*/
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nblks = request_smp_blocks(plane, fb->pixel_format, nplanes, src_w);
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if (nblks < 0)
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return nblks;
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/*
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* Currently we update the hw for allocations/requests immediately,
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* but once atomic modeset/pageflip is in place, the allocation
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* would move into atomic->check_plane_state(), while updating the
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* hw would remain here:
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*/
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for (i = 0; i < pipe2nclients(pipe); i++)
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mdp5_smp_configure(mdp5_kms, pipe2client(pipe, i));
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if (src_w != crtc_w) {
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config |= MDP5_PIPE_SCALE_CONFIG_SCALEX_EN;
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/* TODO calc phasex_step, hdecm */
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}
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if (src_h != crtc_h) {
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config |= MDP5_PIPE_SCALE_CONFIG_SCALEY_EN;
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/* TODO calc phasey_step, vdecm */
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}
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mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_IMG_SIZE(pipe),
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MDP5_PIPE_SRC_IMG_SIZE_WIDTH(src_w) |
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MDP5_PIPE_SRC_IMG_SIZE_HEIGHT(src_h));
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mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_SIZE(pipe),
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MDP5_PIPE_SRC_SIZE_WIDTH(src_w) |
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MDP5_PIPE_SRC_SIZE_HEIGHT(src_h));
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mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_XY(pipe),
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MDP5_PIPE_SRC_XY_X(src_x) |
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MDP5_PIPE_SRC_XY_Y(src_y));
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mdp5_write(mdp5_kms, REG_MDP5_PIPE_OUT_SIZE(pipe),
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MDP5_PIPE_OUT_SIZE_WIDTH(crtc_w) |
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MDP5_PIPE_OUT_SIZE_HEIGHT(crtc_h));
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mdp5_write(mdp5_kms, REG_MDP5_PIPE_OUT_XY(pipe),
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MDP5_PIPE_OUT_XY_X(crtc_x) |
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MDP5_PIPE_OUT_XY_Y(crtc_y));
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mdp5_plane_set_scanout(plane, fb);
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format = to_mdp_format(msm_framebuffer_format(fb));
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mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_FORMAT(pipe),
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MDP5_PIPE_SRC_FORMAT_A_BPC(format->bpc_a) |
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MDP5_PIPE_SRC_FORMAT_R_BPC(format->bpc_r) |
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MDP5_PIPE_SRC_FORMAT_G_BPC(format->bpc_g) |
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MDP5_PIPE_SRC_FORMAT_B_BPC(format->bpc_b) |
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COND(format->alpha_enable, MDP5_PIPE_SRC_FORMAT_ALPHA_ENABLE) |
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MDP5_PIPE_SRC_FORMAT_CPP(format->cpp - 1) |
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MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(format->unpack_count - 1) |
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COND(format->unpack_tight, MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT) |
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MDP5_PIPE_SRC_FORMAT_NUM_PLANES(nplanes - 1) |
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MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(CHROMA_RGB));
|
|
|
|
|
|
|
|
mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_UNPACK(pipe),
|
|
|
|
MDP5_PIPE_SRC_UNPACK_ELEM0(format->unpack[0]) |
|
|
|
|
MDP5_PIPE_SRC_UNPACK_ELEM1(format->unpack[1]) |
|
|
|
|
MDP5_PIPE_SRC_UNPACK_ELEM2(format->unpack[2]) |
|
|
|
|
MDP5_PIPE_SRC_UNPACK_ELEM3(format->unpack[3]));
|
|
|
|
|
|
|
|
mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_OP_MODE(pipe),
|
|
|
|
MDP5_PIPE_SRC_OP_MODE_BWC(BWC_LOSSLESS));
|
|
|
|
|
|
|
|
/* not using secure mode: */
|
|
|
|
mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(pipe), 0);
|
|
|
|
|
|
|
|
mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_X(pipe), phasex_step);
|
|
|
|
mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(pipe), phasey_step);
|
|
|
|
mdp5_write(mdp5_kms, REG_MDP5_PIPE_DECIMATION(pipe),
|
|
|
|
MDP5_PIPE_DECIMATION_VERT(vdecm) |
|
|
|
|
MDP5_PIPE_DECIMATION_HORZ(hdecm));
|
|
|
|
mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CONFIG(pipe),
|
|
|
|
MDP5_PIPE_SCALE_CONFIG_SCALEX_MIN_FILTER(SCALE_FILTER_NEAREST) |
|
|
|
|
MDP5_PIPE_SCALE_CONFIG_SCALEY_MIN_FILTER(SCALE_FILTER_NEAREST) |
|
|
|
|
MDP5_PIPE_SCALE_CONFIG_SCALEX_CR_FILTER(SCALE_FILTER_NEAREST) |
|
|
|
|
MDP5_PIPE_SCALE_CONFIG_SCALEY_CR_FILTER(SCALE_FILTER_NEAREST) |
|
|
|
|
MDP5_PIPE_SCALE_CONFIG_SCALEX_MAX_FILTER(SCALE_FILTER_NEAREST) |
|
|
|
|
MDP5_PIPE_SCALE_CONFIG_SCALEY_MAX_FILTER(SCALE_FILTER_NEAREST));
|
|
|
|
|
|
|
|
set_fifo_thresholds(plane, nblks);
|
|
|
|
|
|
|
|
/* TODO detach from old crtc (if we had more than one) */
|
|
|
|
mdp5_crtc_attach(crtc, plane);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void mdp5_plane_complete_flip(struct drm_plane *plane)
|
|
|
|
{
|
|
|
|
struct mdp5_kms *mdp5_kms = get_kms(plane);
|
|
|
|
enum mdp5_pipe pipe = to_mdp5_plane(plane)->pipe;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < pipe2nclients(pipe); i++)
|
|
|
|
mdp5_smp_commit(mdp5_kms, pipe2client(pipe, i));
|
|
|
|
}
|
|
|
|
|
|
|
|
enum mdp5_pipe mdp5_plane_pipe(struct drm_plane *plane)
|
|
|
|
{
|
|
|
|
struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
|
|
|
|
return mdp5_plane->pipe;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* initialize plane */
|
|
|
|
struct drm_plane *mdp5_plane_init(struct drm_device *dev,
|
|
|
|
enum mdp5_pipe pipe, bool private_plane)
|
|
|
|
{
|
|
|
|
struct drm_plane *plane = NULL;
|
|
|
|
struct mdp5_plane *mdp5_plane;
|
|
|
|
int ret;
|
2014-04-01 15:22:39 -07:00
|
|
|
enum drm_plane_type type;
|
drm/msm: add mdp5/apq8x74
Add support for the new MDP5 display controller block. The mapping
between parts of the display controller and KMS is:
plane -> PIPE{RGBn,VIGn} \
crtc -> LM (layer mixer) |-> MDP "device"
encoder -> INTF /
connector -> HDMI/DSI/eDP/etc --> other device(s)
Unlike MDP4, it appears we can get by with a single encoder, rather
than needing a different implementation for DTV, DSI, etc. (Ie. the
register interface is same, just different bases.)
Also unlike MDP4, all the IRQs for other blocks (HDMI, DSI, etc) are
routed through MDP.
And finally, MDP5 has this "Shared Memory Pool" (called "SMP"), from
which blocks need to be allocated to the active pipes based on fetch
stride.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-11-30 17:51:47 -05:00
|
|
|
|
|
|
|
mdp5_plane = kzalloc(sizeof(*mdp5_plane), GFP_KERNEL);
|
|
|
|
if (!mdp5_plane) {
|
|
|
|
ret = -ENOMEM;
|
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
|
|
|
|
plane = &mdp5_plane->base;
|
|
|
|
|
|
|
|
mdp5_plane->pipe = pipe;
|
|
|
|
mdp5_plane->name = pipe2name(pipe);
|
|
|
|
|
|
|
|
mdp5_plane->nformats = mdp5_get_formats(pipe, mdp5_plane->formats,
|
|
|
|
ARRAY_SIZE(mdp5_plane->formats));
|
|
|
|
|
2014-04-01 15:22:39 -07:00
|
|
|
type = private_plane ? DRM_PLANE_TYPE_PRIMARY : DRM_PLANE_TYPE_OVERLAY;
|
|
|
|
drm_universal_plane_init(dev, plane, 0xff, &mdp5_plane_funcs,
|
|
|
|
mdp5_plane->formats, mdp5_plane->nformats,
|
|
|
|
type);
|
drm/msm: add mdp5/apq8x74
Add support for the new MDP5 display controller block. The mapping
between parts of the display controller and KMS is:
plane -> PIPE{RGBn,VIGn} \
crtc -> LM (layer mixer) |-> MDP "device"
encoder -> INTF /
connector -> HDMI/DSI/eDP/etc --> other device(s)
Unlike MDP4, it appears we can get by with a single encoder, rather
than needing a different implementation for DTV, DSI, etc. (Ie. the
register interface is same, just different bases.)
Also unlike MDP4, all the IRQs for other blocks (HDMI, DSI, etc) are
routed through MDP.
And finally, MDP5 has this "Shared Memory Pool" (called "SMP"), from
which blocks need to be allocated to the active pipes based on fetch
stride.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-11-30 17:51:47 -05:00
|
|
|
|
|
|
|
mdp5_plane_install_properties(plane, &plane->base);
|
|
|
|
|
|
|
|
return plane;
|
|
|
|
|
|
|
|
fail:
|
|
|
|
if (plane)
|
|
|
|
mdp5_plane_destroy(plane);
|
|
|
|
|
|
|
|
return ERR_PTR(ret);
|
|
|
|
}
|