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								/* ns87303.h: Configuration Register Description for the
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								 *            National Semiconductor PC87303 (SuperIO).
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								 *
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								 * Copyright (C) 1997  Eddie C. Dost  (ecd@skynet.be)
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								 */
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								#ifndef _SPARC_NS87303_H
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								#define _SPARC_NS87303_H 1
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								/*
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								 * Control Register Index Values
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								 */
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								#define FER	0x00
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								#define FAR	0x01
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								#define PTR	0x02
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								#define FCR	0x03
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								#define PCR	0x04
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								#define KRR	0x05
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								#define PMC	0x06
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								#define TUP	0x07
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								#define SID	0x08
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								#define ASC	0x09
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								#define CS0CF0	0x0a
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								#define CS0CF1	0x0b
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								#define CS1CF0	0x0c
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								#define CS1CF1	0x0d
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								/* Function Enable Register (FER) bits */
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								#define FER_EDM		0x10	/* Encoded Drive and Motor pin information   */
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								/* Function Address Register (FAR) bits */
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								#define FAR_LPT_MASK	0x03
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								#define FAR_LPTB	0x00
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								#define FAR_LPTA	0x01
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								#define FAR_LPTC	0x02
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								/* Power and Test Register (PTR) bits */
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								#define PTR_LPTB_IRQ7	0x08
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								#define PTR_LEVEL_IRQ	0x80	/* When not ECP/EPP: Use level IRQ           */
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								#define PTR_LPT_REG_DIR	0x80	/* When ECP/EPP: LPT CTR controlls direction */
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												/*               of the parallel port	     */
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								/* Function Control Register (FCR) bits */
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								#define FCR_LDE		0x10	/* Logical Drive Exchange                    */
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								#define FCR_ZWS_ENA	0x20	/* Enable short host read/write in ECP/EPP   */
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								/* Printer Control Register (PCR) bits */
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								#define PCR_EPP_ENABLE	0x01
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								#define PCR_EPP_IEEE	0x02	/* Enable EPP Version 1.9 (IEEE 1284)        */
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								#define PCR_ECP_ENABLE	0x04
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								#define PCR_ECP_CLK_ENA	0x08	/* If 0 ECP Clock is stopped on Power down   */
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								#define PCR_IRQ_POLAR	0x20	/* If 0 IRQ is level high or negative pulse, */
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												/* if 1 polarity is inverted                 */
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								#define PCR_IRQ_ODRAIN	0x40	/* If 1, IRQ is open drain                   */
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								/* Tape UARTs and Parallel Port Config Register (TUP) bits */
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								#define TUP_EPP_TIMO	0x02	/* Enable EPP timeout IRQ                    */
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								/* Advanced SuperIO Config Register (ASC) bits */
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								#define ASC_LPT_IRQ7	0x01	/* Always use IRQ7 for LPT                  */
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								#define ASC_DRV2_SEL	0x02	/* Logical Drive Exchange controlled by TDR  */
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								#define FER_RESERVED	0x00
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								#define FAR_RESERVED	0x00
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								#define PTR_RESERVED	0x73
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								#define FCR_RESERVED	0xc4
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								#define PCR_RESERVED	0x10
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								#define KRR_RESERVED	0x00
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								#define PMC_RESERVED	0x98
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								#define TUP_RESERVED	0xfb
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								#define SIP_RESERVED	0x00
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								#define ASC_RESERVED	0x18
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								#define CS0CF0_RESERVED	0x00
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								#define CS0CF1_RESERVED	0x08
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								#define CS1CF0_RESERVED	0x00
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								#define CS1CF1_RESERVED	0x08
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								#ifdef __KERNEL__
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								#include <linux/spinlock.h>
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								#include <asm/system.h>
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								#include <asm/io.h>
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								extern spinlock_t ns87303_lock;
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								static inline int ns87303_modify(unsigned long port, unsigned int index,
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												     unsigned char clr, unsigned char set)
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								{
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									static unsigned char reserved[] = {
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										FER_RESERVED, FAR_RESERVED, PTR_RESERVED, FCR_RESERVED,
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										PCR_RESERVED, KRR_RESERVED, PMC_RESERVED, TUP_RESERVED,
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										SIP_RESERVED, ASC_RESERVED, CS0CF0_RESERVED, CS0CF1_RESERVED,
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										CS1CF0_RESERVED, CS1CF1_RESERVED
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									};
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									unsigned long flags;
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									unsigned char value;
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									if (index > 0x0d)
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										return -EINVAL;
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									spin_lock_irqsave(&ns87303_lock, flags);
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									outb(index, port);
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									value = inb(port + 1);
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									value &= ~(reserved[index] | clr);
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									value |= set;
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									outb(value, port + 1);
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									outb(value, port + 1);
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									spin_unlock_irqrestore(&ns87303_lock, flags);
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									return 0;
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								}
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								#endif /* __KERNEL__ */
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								#endif /* !(_SPARC_NS87303_H) */
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