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linux-pinenote/arch/tile/include/gxio/iorpc_trio.h

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arch/tile: provide kernel support for the tilegx TRIO shim Provide kernel support for the tilegx "Transaction I/O" (TRIO) on-chip hardware. This hardware implements the PCIe interface for tilegx; the driver changes to use TRIO for PCIe are in a subsequent commit. The change is layered on top of the tilegx GXIO IORPC subsystem. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
2012-04-07 16:53:03 -04:00
/*
* Copyright 2012 Tilera Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation, version 2.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
* NON INFRINGEMENT. See the GNU General Public License for
* more details.
*/
/* This file is machine-generated; DO NOT EDIT! */
#ifndef __GXIO_TRIO_LINUX_RPC_H__
#define __GXIO_TRIO_LINUX_RPC_H__
#include <hv/iorpc.h>
#include <hv/drv_trio_intf.h>
#include <gxio/trio.h>
#include <gxio/kiorpc.h>
#include <linux/string.h>
#include <linux/module.h>
#include <asm/pgtable.h>
tile: gxio iorpc numbering change for TRIO interface An ABI numbering change was made in the hypervisor for Tilera's 4.1 MDE release (just shipped). It's incompatible with the previous 4.0 release ABI numbering, so we track the new numbering going forward. We plan to avoid modifying ABI numbering for these interfaces again. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
2012-09-24 14:57:58 -04:00
#define GXIO_TRIO_OP_DEALLOC_ASID IORPC_OPCODE(IORPC_FORMAT_NONE, 0x1400)
#define GXIO_TRIO_OP_ALLOC_ASIDS IORPC_OPCODE(IORPC_FORMAT_NONE, 0x1401)
arch/tile: provide kernel support for the tilegx TRIO shim Provide kernel support for the tilegx "Transaction I/O" (TRIO) on-chip hardware. This hardware implements the PCIe interface for tilegx; the driver changes to use TRIO for PCIe are in a subsequent commit. The change is layered on top of the tilegx GXIO IORPC subsystem. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
2012-04-07 16:53:03 -04:00
tile: gxio iorpc numbering change for TRIO interface An ABI numbering change was made in the hypervisor for Tilera's 4.1 MDE release (just shipped). It's incompatible with the previous 4.0 release ABI numbering, so we track the new numbering going forward. We plan to avoid modifying ABI numbering for these interfaces again. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
2012-09-24 14:57:58 -04:00
#define GXIO_TRIO_OP_ALLOC_MEMORY_MAPS IORPC_OPCODE(IORPC_FORMAT_NONE, 0x1404)
arch/tile: provide kernel support for the tilegx TRIO shim Provide kernel support for the tilegx "Transaction I/O" (TRIO) on-chip hardware. This hardware implements the PCIe interface for tilegx; the driver changes to use TRIO for PCIe are in a subsequent commit. The change is layered on top of the tilegx GXIO IORPC subsystem. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
2012-04-07 16:53:03 -04:00
tile PCI RC: support more MSI-X interrupt vectors To support PCIe devices with higher number of MSI-X interrupt vectors, e.g. 16 for the LSI RAID card, enhance the Gx RC stack to provide more MSI-X vectors by using the TRIO Scatter Queues, which provide 8 more vectors in addition to ~10 from the Map Mem regions. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
2013-08-02 12:55:15 -04:00
#define GXIO_TRIO_OP_ALLOC_SCATTER_QUEUES IORPC_OPCODE(IORPC_FORMAT_NONE, 0x140e)
tile: gxio iorpc numbering change for TRIO interface An ABI numbering change was made in the hypervisor for Tilera's 4.1 MDE release (just shipped). It's incompatible with the previous 4.0 release ABI numbering, so we track the new numbering going forward. We plan to avoid modifying ABI numbering for these interfaces again. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
2012-09-24 14:57:58 -04:00
#define GXIO_TRIO_OP_ALLOC_PIO_REGIONS IORPC_OPCODE(IORPC_FORMAT_NONE, 0x1412)
arch/tile: provide kernel support for the tilegx TRIO shim Provide kernel support for the tilegx "Transaction I/O" (TRIO) on-chip hardware. This hardware implements the PCIe interface for tilegx; the driver changes to use TRIO for PCIe are in a subsequent commit. The change is layered on top of the tilegx GXIO IORPC subsystem. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
2012-04-07 16:53:03 -04:00
tile: gxio iorpc numbering change for TRIO interface An ABI numbering change was made in the hypervisor for Tilera's 4.1 MDE release (just shipped). It's incompatible with the previous 4.0 release ABI numbering, so we track the new numbering going forward. We plan to avoid modifying ABI numbering for these interfaces again. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
2012-09-24 14:57:58 -04:00
#define GXIO_TRIO_OP_INIT_PIO_REGION_AUX IORPC_OPCODE(IORPC_FORMAT_NONE, 0x1414)
arch/tile: provide kernel support for the tilegx TRIO shim Provide kernel support for the tilegx "Transaction I/O" (TRIO) on-chip hardware. This hardware implements the PCIe interface for tilegx; the driver changes to use TRIO for PCIe are in a subsequent commit. The change is layered on top of the tilegx GXIO IORPC subsystem. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
2012-04-07 16:53:03 -04:00
tile: gxio iorpc numbering change for TRIO interface An ABI numbering change was made in the hypervisor for Tilera's 4.1 MDE release (just shipped). It's incompatible with the previous 4.0 release ABI numbering, so we track the new numbering going forward. We plan to avoid modifying ABI numbering for these interfaces again. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
2012-09-24 14:57:58 -04:00
#define GXIO_TRIO_OP_INIT_MEMORY_MAP_MMU_AUX IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x141e)
#define GXIO_TRIO_OP_GET_PORT_PROPERTY IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x141f)
#define GXIO_TRIO_OP_CONFIG_LEGACY_INTR IORPC_OPCODE(IORPC_FORMAT_KERNEL_INTERRUPT, 0x1420)
#define GXIO_TRIO_OP_CONFIG_MSI_INTR IORPC_OPCODE(IORPC_FORMAT_KERNEL_INTERRUPT, 0x1421)
#define GXIO_TRIO_OP_SET_MPS_MRS IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x1423)
#define GXIO_TRIO_OP_FORCE_RC_LINK_UP IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x1424)
#define GXIO_TRIO_OP_FORCE_EP_LINK_UP IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x1425)
arch/tile: provide kernel support for the tilegx TRIO shim Provide kernel support for the tilegx "Transaction I/O" (TRIO) on-chip hardware. This hardware implements the PCIe interface for tilegx; the driver changes to use TRIO for PCIe are in a subsequent commit. The change is layered on top of the tilegx GXIO IORPC subsystem. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
2012-04-07 16:53:03 -04:00
#define GXIO_TRIO_OP_GET_MMIO_BASE IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x8000)
#define GXIO_TRIO_OP_CHECK_MMIO_OFFSET IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x8001)
tile: improve gxio iorpc autogenerated code style Fix some whitespace style issues in some auto-generated files. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
2013-09-16 13:52:45 -04:00
int gxio_trio_alloc_asids(gxio_trio_context_t *context, unsigned int count,
arch/tile: provide kernel support for the tilegx TRIO shim Provide kernel support for the tilegx "Transaction I/O" (TRIO) on-chip hardware. This hardware implements the PCIe interface for tilegx; the driver changes to use TRIO for PCIe are in a subsequent commit. The change is layered on top of the tilegx GXIO IORPC subsystem. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
2012-04-07 16:53:03 -04:00
unsigned int first, unsigned int flags);
tile: improve gxio iorpc autogenerated code style Fix some whitespace style issues in some auto-generated files. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
2013-09-16 13:52:45 -04:00
int gxio_trio_alloc_memory_maps(gxio_trio_context_t *context,
arch/tile: provide kernel support for the tilegx TRIO shim Provide kernel support for the tilegx "Transaction I/O" (TRIO) on-chip hardware. This hardware implements the PCIe interface for tilegx; the driver changes to use TRIO for PCIe are in a subsequent commit. The change is layered on top of the tilegx GXIO IORPC subsystem. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
2012-04-07 16:53:03 -04:00
unsigned int count, unsigned int first,
unsigned int flags);
tile: improve gxio iorpc autogenerated code style Fix some whitespace style issues in some auto-generated files. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
2013-09-16 13:52:45 -04:00
int gxio_trio_alloc_scatter_queues(gxio_trio_context_t *context,
tile PCI RC: support more MSI-X interrupt vectors To support PCIe devices with higher number of MSI-X interrupt vectors, e.g. 16 for the LSI RAID card, enhance the Gx RC stack to provide more MSI-X vectors by using the TRIO Scatter Queues, which provide 8 more vectors in addition to ~10 from the Map Mem regions. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
2013-08-02 12:55:15 -04:00
unsigned int count, unsigned int first,
unsigned int flags);
tile: improve gxio iorpc autogenerated code style Fix some whitespace style issues in some auto-generated files. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
2013-09-16 13:52:45 -04:00
int gxio_trio_alloc_pio_regions(gxio_trio_context_t *context,
arch/tile: provide kernel support for the tilegx TRIO shim Provide kernel support for the tilegx "Transaction I/O" (TRIO) on-chip hardware. This hardware implements the PCIe interface for tilegx; the driver changes to use TRIO for PCIe are in a subsequent commit. The change is layered on top of the tilegx GXIO IORPC subsystem. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
2012-04-07 16:53:03 -04:00
unsigned int count, unsigned int first,
unsigned int flags);
tile: improve gxio iorpc autogenerated code style Fix some whitespace style issues in some auto-generated files. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
2013-09-16 13:52:45 -04:00
int gxio_trio_init_pio_region_aux(gxio_trio_context_t *context,
arch/tile: provide kernel support for the tilegx TRIO shim Provide kernel support for the tilegx "Transaction I/O" (TRIO) on-chip hardware. This hardware implements the PCIe interface for tilegx; the driver changes to use TRIO for PCIe are in a subsequent commit. The change is layered on top of the tilegx GXIO IORPC subsystem. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
2012-04-07 16:53:03 -04:00
unsigned int pio_region, unsigned int mac,
uint32_t bus_address_hi, unsigned int flags);
tile: improve gxio iorpc autogenerated code style Fix some whitespace style issues in some auto-generated files. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
2013-09-16 13:52:45 -04:00
int gxio_trio_init_memory_map_mmu_aux(gxio_trio_context_t *context,
arch/tile: provide kernel support for the tilegx TRIO shim Provide kernel support for the tilegx "Transaction I/O" (TRIO) on-chip hardware. This hardware implements the PCIe interface for tilegx; the driver changes to use TRIO for PCIe are in a subsequent commit. The change is layered on top of the tilegx GXIO IORPC subsystem. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
2012-04-07 16:53:03 -04:00
unsigned int map, unsigned long va,
uint64_t size, unsigned int asid,
unsigned int mac, uint64_t bus_address,
unsigned int node,
unsigned int order_mode);
tile: improve gxio iorpc autogenerated code style Fix some whitespace style issues in some auto-generated files. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
2013-09-16 13:52:45 -04:00
int gxio_trio_get_port_property(gxio_trio_context_t *context,
arch/tile: provide kernel support for the tilegx TRIO shim Provide kernel support for the tilegx "Transaction I/O" (TRIO) on-chip hardware. This hardware implements the PCIe interface for tilegx; the driver changes to use TRIO for PCIe are in a subsequent commit. The change is layered on top of the tilegx GXIO IORPC subsystem. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
2012-04-07 16:53:03 -04:00
struct pcie_trio_ports_property *trio_ports);
tile: improve gxio iorpc autogenerated code style Fix some whitespace style issues in some auto-generated files. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
2013-09-16 13:52:45 -04:00
int gxio_trio_config_legacy_intr(gxio_trio_context_t *context, int inter_x,
arch/tile: provide kernel support for the tilegx TRIO shim Provide kernel support for the tilegx "Transaction I/O" (TRIO) on-chip hardware. This hardware implements the PCIe interface for tilegx; the driver changes to use TRIO for PCIe are in a subsequent commit. The change is layered on top of the tilegx GXIO IORPC subsystem. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
2012-04-07 16:53:03 -04:00
int inter_y, int inter_ipi, int inter_event,
unsigned int mac, unsigned int intx);
tile: improve gxio iorpc autogenerated code style Fix some whitespace style issues in some auto-generated files. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
2013-09-16 13:52:45 -04:00
int gxio_trio_config_msi_intr(gxio_trio_context_t *context, int inter_x,
arch/tile: provide kernel support for the tilegx TRIO shim Provide kernel support for the tilegx "Transaction I/O" (TRIO) on-chip hardware. This hardware implements the PCIe interface for tilegx; the driver changes to use TRIO for PCIe are in a subsequent commit. The change is layered on top of the tilegx GXIO IORPC subsystem. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
2012-04-07 16:53:03 -04:00
int inter_y, int inter_ipi, int inter_event,
unsigned int mac, unsigned int mem_map,
uint64_t mem_map_base, uint64_t mem_map_limit,
unsigned int asid);
tile: improve gxio iorpc autogenerated code style Fix some whitespace style issues in some auto-generated files. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
2013-09-16 13:52:45 -04:00
int gxio_trio_set_mps_mrs(gxio_trio_context_t *context, uint16_t mps,
arch/tile: provide kernel support for the tilegx TRIO shim Provide kernel support for the tilegx "Transaction I/O" (TRIO) on-chip hardware. This hardware implements the PCIe interface for tilegx; the driver changes to use TRIO for PCIe are in a subsequent commit. The change is layered on top of the tilegx GXIO IORPC subsystem. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
2012-04-07 16:53:03 -04:00
uint16_t mrs, unsigned int mac);
tile: improve gxio iorpc autogenerated code style Fix some whitespace style issues in some auto-generated files. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
2013-09-16 13:52:45 -04:00
int gxio_trio_force_rc_link_up(gxio_trio_context_t *context, unsigned int mac);
arch/tile: provide kernel support for the tilegx TRIO shim Provide kernel support for the tilegx "Transaction I/O" (TRIO) on-chip hardware. This hardware implements the PCIe interface for tilegx; the driver changes to use TRIO for PCIe are in a subsequent commit. The change is layered on top of the tilegx GXIO IORPC subsystem. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
2012-04-07 16:53:03 -04:00
tile: improve gxio iorpc autogenerated code style Fix some whitespace style issues in some auto-generated files. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
2013-09-16 13:52:45 -04:00
int gxio_trio_force_ep_link_up(gxio_trio_context_t *context, unsigned int mac);
arch/tile: provide kernel support for the tilegx TRIO shim Provide kernel support for the tilegx "Transaction I/O" (TRIO) on-chip hardware. This hardware implements the PCIe interface for tilegx; the driver changes to use TRIO for PCIe are in a subsequent commit. The change is layered on top of the tilegx GXIO IORPC subsystem. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
2012-04-07 16:53:03 -04:00
tile: improve gxio iorpc autogenerated code style Fix some whitespace style issues in some auto-generated files. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
2013-09-16 13:52:45 -04:00
int gxio_trio_get_mmio_base(gxio_trio_context_t *context, HV_PTE *base);
arch/tile: provide kernel support for the tilegx TRIO shim Provide kernel support for the tilegx "Transaction I/O" (TRIO) on-chip hardware. This hardware implements the PCIe interface for tilegx; the driver changes to use TRIO for PCIe are in a subsequent commit. The change is layered on top of the tilegx GXIO IORPC subsystem. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
2012-04-07 16:53:03 -04:00
tile: improve gxio iorpc autogenerated code style Fix some whitespace style issues in some auto-generated files. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
2013-09-16 13:52:45 -04:00
int gxio_trio_check_mmio_offset(gxio_trio_context_t *context,
arch/tile: provide kernel support for the tilegx TRIO shim Provide kernel support for the tilegx "Transaction I/O" (TRIO) on-chip hardware. This hardware implements the PCIe interface for tilegx; the driver changes to use TRIO for PCIe are in a subsequent commit. The change is layered on top of the tilegx GXIO IORPC subsystem. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
2012-04-07 16:53:03 -04:00
unsigned long offset, unsigned long size);
#endif /* !__GXIO_TRIO_LINUX_RPC_H__ */
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