390 lines
10 KiB
C
390 lines
10 KiB
C
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/* Applied Micro X-Gene SoC Ethernet Driver
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*
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* Copyright (c) 2014, Applied Micro Circuits Corporation
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* Authors: Iyappan Subramanian <isubramanian@apm.com>
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* Keyur Chudgar <kchudgar@apm.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "xgene_enet_main.h"
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#include "xgene_enet_hw.h"
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#include "xgene_enet_sgmac.h"
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static void xgene_enet_wr_csr(struct xgene_enet_pdata *p, u32 offset, u32 val)
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{
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iowrite32(val, p->eth_csr_addr + offset);
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}
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static void xgene_enet_wr_ring_if(struct xgene_enet_pdata *p,
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u32 offset, u32 val)
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{
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iowrite32(val, p->eth_ring_if_addr + offset);
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}
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static void xgene_enet_wr_diag_csr(struct xgene_enet_pdata *p,
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u32 offset, u32 val)
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{
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iowrite32(val, p->eth_diag_csr_addr + offset);
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}
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static bool xgene_enet_wr_indirect(struct xgene_indirect_ctl *ctl,
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u32 wr_addr, u32 wr_data)
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{
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int i;
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iowrite32(wr_addr, ctl->addr);
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iowrite32(wr_data, ctl->ctl);
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iowrite32(XGENE_ENET_WR_CMD, ctl->cmd);
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/* wait for write command to complete */
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for (i = 0; i < 10; i++) {
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if (ioread32(ctl->cmd_done)) {
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iowrite32(0, ctl->cmd);
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return true;
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}
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udelay(1);
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}
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return false;
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}
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static void xgene_enet_wr_mac(struct xgene_enet_pdata *p,
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u32 wr_addr, u32 wr_data)
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{
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struct xgene_indirect_ctl ctl = {
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.addr = p->mcx_mac_addr + MAC_ADDR_REG_OFFSET,
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.ctl = p->mcx_mac_addr + MAC_WRITE_REG_OFFSET,
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.cmd = p->mcx_mac_addr + MAC_COMMAND_REG_OFFSET,
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.cmd_done = p->mcx_mac_addr + MAC_COMMAND_DONE_REG_OFFSET
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};
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if (!xgene_enet_wr_indirect(&ctl, wr_addr, wr_data))
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netdev_err(p->ndev, "mac write failed, addr: %04x\n", wr_addr);
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}
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static u32 xgene_enet_rd_csr(struct xgene_enet_pdata *p, u32 offset)
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{
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return ioread32(p->eth_csr_addr + offset);
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}
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static u32 xgene_enet_rd_diag_csr(struct xgene_enet_pdata *p, u32 offset)
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{
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return ioread32(p->eth_diag_csr_addr + offset);
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}
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static u32 xgene_enet_rd_indirect(struct xgene_indirect_ctl *ctl, u32 rd_addr)
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{
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u32 rd_data;
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int i;
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iowrite32(rd_addr, ctl->addr);
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iowrite32(XGENE_ENET_RD_CMD, ctl->cmd);
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/* wait for read command to complete */
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for (i = 0; i < 10; i++) {
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if (ioread32(ctl->cmd_done)) {
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rd_data = ioread32(ctl->ctl);
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iowrite32(0, ctl->cmd);
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return rd_data;
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}
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udelay(1);
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}
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pr_err("%s: mac read failed, addr: %04x\n", __func__, rd_addr);
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return 0;
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}
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static u32 xgene_enet_rd_mac(struct xgene_enet_pdata *p, u32 rd_addr)
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{
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struct xgene_indirect_ctl ctl = {
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.addr = p->mcx_mac_addr + MAC_ADDR_REG_OFFSET,
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.ctl = p->mcx_mac_addr + MAC_READ_REG_OFFSET,
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.cmd = p->mcx_mac_addr + MAC_COMMAND_REG_OFFSET,
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.cmd_done = p->mcx_mac_addr + MAC_COMMAND_DONE_REG_OFFSET
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};
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return xgene_enet_rd_indirect(&ctl, rd_addr);
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}
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static int xgene_enet_ecc_init(struct xgene_enet_pdata *p)
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{
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struct net_device *ndev = p->ndev;
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u32 data;
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int i;
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xgene_enet_wr_diag_csr(p, ENET_CFG_MEM_RAM_SHUTDOWN_ADDR, 0);
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for (i = 0; i < 10 && data != ~0U ; i++) {
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usleep_range(100, 110);
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data = xgene_enet_rd_diag_csr(p, ENET_BLOCK_MEM_RDY_ADDR);
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}
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if (data != ~0U) {
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netdev_err(ndev, "Failed to release memory from shutdown\n");
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return -ENODEV;
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}
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return 0;
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}
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static void xgene_enet_config_ring_if_assoc(struct xgene_enet_pdata *p)
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{
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u32 val = 0xffffffff;
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xgene_enet_wr_ring_if(p, ENET_CFGSSQMIWQASSOC_ADDR, val);
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xgene_enet_wr_ring_if(p, ENET_CFGSSQMIFPQASSOC_ADDR, val);
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}
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static void xgene_mii_phy_write(struct xgene_enet_pdata *p, u8 phy_id,
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u32 reg, u16 data)
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{
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u32 addr, wr_data, done;
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int i;
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addr = PHY_ADDR(phy_id) | REG_ADDR(reg);
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xgene_enet_wr_mac(p, MII_MGMT_ADDRESS_ADDR, addr);
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wr_data = PHY_CONTROL(data);
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xgene_enet_wr_mac(p, MII_MGMT_CONTROL_ADDR, wr_data);
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for (i = 0; i < 10; i++) {
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done = xgene_enet_rd_mac(p, MII_MGMT_INDICATORS_ADDR);
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if (!(done & BUSY_MASK))
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return;
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usleep_range(10, 20);
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}
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netdev_err(p->ndev, "MII_MGMT write failed\n");
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}
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static u32 xgene_mii_phy_read(struct xgene_enet_pdata *p, u8 phy_id, u32 reg)
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{
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u32 addr, data, done;
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int i;
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addr = PHY_ADDR(phy_id) | REG_ADDR(reg);
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xgene_enet_wr_mac(p, MII_MGMT_ADDRESS_ADDR, addr);
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xgene_enet_wr_mac(p, MII_MGMT_COMMAND_ADDR, READ_CYCLE_MASK);
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for (i = 0; i < 10; i++) {
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done = xgene_enet_rd_mac(p, MII_MGMT_INDICATORS_ADDR);
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if (!(done & BUSY_MASK)) {
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data = xgene_enet_rd_mac(p, MII_MGMT_STATUS_ADDR);
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xgene_enet_wr_mac(p, MII_MGMT_COMMAND_ADDR, 0);
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return data;
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}
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usleep_range(10, 20);
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}
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netdev_err(p->ndev, "MII_MGMT read failed\n");
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return 0;
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}
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static void xgene_sgmac_reset(struct xgene_enet_pdata *p)
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{
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xgene_enet_wr_mac(p, MAC_CONFIG_1_ADDR, SOFT_RESET1);
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xgene_enet_wr_mac(p, MAC_CONFIG_1_ADDR, 0);
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}
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static void xgene_sgmac_set_mac_addr(struct xgene_enet_pdata *p)
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{
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u32 addr0, addr1;
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u8 *dev_addr = p->ndev->dev_addr;
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addr0 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
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(dev_addr[1] << 8) | dev_addr[0];
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xgene_enet_wr_mac(p, STATION_ADDR0_ADDR, addr0);
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addr1 = xgene_enet_rd_mac(p, STATION_ADDR1_ADDR);
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addr1 |= (dev_addr[5] << 24) | (dev_addr[4] << 16);
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xgene_enet_wr_mac(p, STATION_ADDR1_ADDR, addr1);
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}
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static u32 xgene_enet_link_status(struct xgene_enet_pdata *p)
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{
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u32 data;
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data = xgene_mii_phy_read(p, INT_PHY_ADDR,
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SGMII_BASE_PAGE_ABILITY_ADDR >> 2);
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return data & LINK_UP;
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}
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static void xgene_sgmac_init(struct xgene_enet_pdata *p)
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{
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u32 data, loop = 10;
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xgene_sgmac_reset(p);
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/* Enable auto-negotiation */
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xgene_mii_phy_write(p, INT_PHY_ADDR, SGMII_CONTROL_ADDR >> 2, 0x1000);
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xgene_mii_phy_write(p, INT_PHY_ADDR, SGMII_TBI_CONTROL_ADDR >> 2, 0);
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while (loop--) {
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data = xgene_mii_phy_read(p, INT_PHY_ADDR,
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SGMII_STATUS_ADDR >> 2);
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if ((data & AUTO_NEG_COMPLETE) && (data & LINK_STATUS))
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break;
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usleep_range(10, 20);
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}
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if (!(data & AUTO_NEG_COMPLETE) || !(data & LINK_STATUS))
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netdev_err(p->ndev, "Auto-negotiation failed\n");
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data = xgene_enet_rd_mac(p, MAC_CONFIG_2_ADDR);
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ENET_INTERFACE_MODE2_SET(&data, 2);
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xgene_enet_wr_mac(p, MAC_CONFIG_2_ADDR, data | FULL_DUPLEX2);
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xgene_enet_wr_mac(p, INTERFACE_CONTROL_ADDR, ENET_GHD_MODE);
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data = xgene_enet_rd_csr(p, ENET_SPARE_CFG_REG_ADDR);
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data |= MPA_IDLE_WITH_QMI_EMPTY;
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xgene_enet_wr_csr(p, ENET_SPARE_CFG_REG_ADDR, data);
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xgene_sgmac_set_mac_addr(p);
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data = xgene_enet_rd_csr(p, DEBUG_REG_ADDR);
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data |= CFG_BYPASS_UNISEC_TX | CFG_BYPASS_UNISEC_RX;
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xgene_enet_wr_csr(p, DEBUG_REG_ADDR, data);
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/* Adjust MDC clock frequency */
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data = xgene_enet_rd_mac(p, MII_MGMT_CONFIG_ADDR);
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MGMT_CLOCK_SEL_SET(&data, 7);
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xgene_enet_wr_mac(p, MII_MGMT_CONFIG_ADDR, data);
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/* Enable drop if bufpool not available */
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data = xgene_enet_rd_csr(p, RSIF_CONFIG_REG_ADDR);
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data |= CFG_RSIF_FPBUFF_TIMEOUT_EN;
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xgene_enet_wr_csr(p, RSIF_CONFIG_REG_ADDR, data);
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/* Rtype should be copied from FP */
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xgene_enet_wr_csr(p, RSIF_RAM_DBG_REG0_ADDR, 0);
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/* Bypass traffic gating */
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xgene_enet_wr_csr(p, CFG_LINK_AGGR_RESUME_0_ADDR, TX_PORT0);
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xgene_enet_wr_csr(p, CFG_BYPASS_ADDR, RESUME_TX);
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xgene_enet_wr_csr(p, SG_RX_DV_GATE_REG_0_ADDR, RESUME_RX0);
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}
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static void xgene_sgmac_rxtx(struct xgene_enet_pdata *p, u32 bits, bool set)
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{
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u32 data;
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data = xgene_enet_rd_mac(p, MAC_CONFIG_1_ADDR);
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if (set)
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data |= bits;
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else
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data &= ~bits;
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xgene_enet_wr_mac(p, MAC_CONFIG_1_ADDR, data);
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}
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static void xgene_sgmac_rx_enable(struct xgene_enet_pdata *p)
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{
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xgene_sgmac_rxtx(p, RX_EN, true);
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}
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static void xgene_sgmac_tx_enable(struct xgene_enet_pdata *p)
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{
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xgene_sgmac_rxtx(p, TX_EN, true);
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}
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static void xgene_sgmac_rx_disable(struct xgene_enet_pdata *p)
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{
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xgene_sgmac_rxtx(p, RX_EN, false);
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}
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static void xgene_sgmac_tx_disable(struct xgene_enet_pdata *p)
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{
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xgene_sgmac_rxtx(p, TX_EN, false);
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}
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static void xgene_enet_reset(struct xgene_enet_pdata *p)
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{
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clk_prepare_enable(p->clk);
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clk_disable_unprepare(p->clk);
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clk_prepare_enable(p->clk);
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xgene_enet_ecc_init(p);
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xgene_enet_config_ring_if_assoc(p);
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}
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static void xgene_enet_cle_bypass(struct xgene_enet_pdata *p,
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u32 dst_ring_num, u16 bufpool_id)
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{
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u32 data, fpsel;
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data = CFG_CLE_BYPASS_EN0;
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xgene_enet_wr_csr(p, CLE_BYPASS_REG0_0_ADDR, data);
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fpsel = xgene_enet_ring_bufnum(bufpool_id) - 0x20;
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data = CFG_CLE_DSTQID0(dst_ring_num) | CFG_CLE_FPSEL0(fpsel);
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xgene_enet_wr_csr(p, CLE_BYPASS_REG1_0_ADDR, data);
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}
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static void xgene_enet_shutdown(struct xgene_enet_pdata *p)
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{
|
||
|
|
clk_disable_unprepare(p->clk);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void xgene_enet_link_state(struct work_struct *work)
|
||
|
|
{
|
||
|
|
struct xgene_enet_pdata *p = container_of(to_delayed_work(work),
|
||
|
|
struct xgene_enet_pdata, link_work);
|
||
|
|
struct net_device *ndev = p->ndev;
|
||
|
|
u32 link, poll_interval;
|
||
|
|
|
||
|
|
link = xgene_enet_link_status(p);
|
||
|
|
if (link) {
|
||
|
|
if (!netif_carrier_ok(ndev)) {
|
||
|
|
netif_carrier_on(ndev);
|
||
|
|
xgene_sgmac_init(p);
|
||
|
|
xgene_sgmac_rx_enable(p);
|
||
|
|
xgene_sgmac_tx_enable(p);
|
||
|
|
netdev_info(ndev, "Link is Up - 1Gbps\n");
|
||
|
|
}
|
||
|
|
poll_interval = PHY_POLL_LINK_ON;
|
||
|
|
} else {
|
||
|
|
if (netif_carrier_ok(ndev)) {
|
||
|
|
xgene_sgmac_rx_disable(p);
|
||
|
|
xgene_sgmac_tx_disable(p);
|
||
|
|
netif_carrier_off(ndev);
|
||
|
|
netdev_info(ndev, "Link is Down\n");
|
||
|
|
}
|
||
|
|
poll_interval = PHY_POLL_LINK_OFF;
|
||
|
|
}
|
||
|
|
|
||
|
|
schedule_delayed_work(&p->link_work, poll_interval);
|
||
|
|
}
|
||
|
|
|
||
|
|
struct xgene_mac_ops xgene_sgmac_ops = {
|
||
|
|
.init = xgene_sgmac_init,
|
||
|
|
.reset = xgene_sgmac_reset,
|
||
|
|
.rx_enable = xgene_sgmac_rx_enable,
|
||
|
|
.tx_enable = xgene_sgmac_tx_enable,
|
||
|
|
.rx_disable = xgene_sgmac_rx_disable,
|
||
|
|
.tx_disable = xgene_sgmac_tx_disable,
|
||
|
|
.set_mac_addr = xgene_sgmac_set_mac_addr,
|
||
|
|
.link_state = xgene_enet_link_state
|
||
|
|
};
|
||
|
|
|
||
|
|
struct xgene_port_ops xgene_sgport_ops = {
|
||
|
|
.reset = xgene_enet_reset,
|
||
|
|
.cle_bypass = xgene_enet_cle_bypass,
|
||
|
|
.shutdown = xgene_enet_shutdown
|
||
|
|
};
|