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linux-pinenote/Documentation/devicetree/bindings/arm/msm/timer.txt

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ARM: msm: Add DT support to msm_timer Add support to setup the MSM timer via information obtained from the devicetree. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> [davidb@codeaurora.org: Remove leading zeros] Signed-off-by: David Brown <davidb@codeaurora.org>
2012-09-05 12:28:53 -07:00
* MSM Timer
Properties:
- compatible : Should at least contain "qcom,msm-timer". More specific
ARM: msm: Rework timer binding to be more general The msm timer binding I wrote is bad. First off, the clock frequency in the binding for the dgt is wrong. Software divides down the input rate by 4 to achieve the rate listed in the binding. We also treat each individual timer as a separate hardware component, when in reality there is one timer block (that may be duplicated per cpu) with multiple timers within it. Depending on the version of the hardware there can be one or two general purpose timers, status and divider control registers, and an entirely different register layout. In the next patch we'll need to know about the different register layouts so that we can properly check the status register after clearing the count. The current binding makes this complicated because the general purpose timer's reg property doesn't indicate where that status register is, and in fact it is beyond the size of the reg property. Clean all this up by just having one node for the timer hardware, and describe all the interrupts and clock frequencies supported while having one reg property that covers the entire timer register region. We'll use the compatible field in the future to determine different register layouts and if we should read the status registers, etc. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: David Brown <davidb@codeaurora.org>
2013-03-14 20:31:38 -07:00
properties specify which subsystem the timers are paired with.
ARM: msm: Add DT support to msm_timer Add support to setup the MSM timer via information obtained from the devicetree. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> [davidb@codeaurora.org: Remove leading zeros] Signed-off-by: David Brown <davidb@codeaurora.org>
2012-09-05 12:28:53 -07:00
ARM: msm: Rework timer binding to be more general The msm timer binding I wrote is bad. First off, the clock frequency in the binding for the dgt is wrong. Software divides down the input rate by 4 to achieve the rate listed in the binding. We also treat each individual timer as a separate hardware component, when in reality there is one timer block (that may be duplicated per cpu) with multiple timers within it. Depending on the version of the hardware there can be one or two general purpose timers, status and divider control registers, and an entirely different register layout. In the next patch we'll need to know about the different register layouts so that we can properly check the status register after clearing the count. The current binding makes this complicated because the general purpose timer's reg property doesn't indicate where that status register is, and in fact it is beyond the size of the reg property. Clean all this up by just having one node for the timer hardware, and describe all the interrupts and clock frequencies supported while having one reg property that covers the entire timer register region. We'll use the compatible field in the future to determine different register layouts and if we should read the status registers, etc. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: David Brown <davidb@codeaurora.org>
2013-03-14 20:31:38 -07:00
"qcom,kpss-timer" - krait subsystem
"qcom,scss-timer" - scorpion subsystem
ARM: msm: Add DT support to msm_timer Add support to setup the MSM timer via information obtained from the devicetree. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> [davidb@codeaurora.org: Remove leading zeros] Signed-off-by: David Brown <davidb@codeaurora.org>
2012-09-05 12:28:53 -07:00
ARM: msm: Rework timer binding to be more general The msm timer binding I wrote is bad. First off, the clock frequency in the binding for the dgt is wrong. Software divides down the input rate by 4 to achieve the rate listed in the binding. We also treat each individual timer as a separate hardware component, when in reality there is one timer block (that may be duplicated per cpu) with multiple timers within it. Depending on the version of the hardware there can be one or two general purpose timers, status and divider control registers, and an entirely different register layout. In the next patch we'll need to know about the different register layouts so that we can properly check the status register after clearing the count. The current binding makes this complicated because the general purpose timer's reg property doesn't indicate where that status register is, and in fact it is beyond the size of the reg property. Clean all this up by just having one node for the timer hardware, and describe all the interrupts and clock frequencies supported while having one reg property that covers the entire timer register region. We'll use the compatible field in the future to determine different register layouts and if we should read the status registers, etc. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: David Brown <davidb@codeaurora.org>
2013-03-14 20:31:38 -07:00
- interrupts : Interrupts for the the debug timer, the first general purpose
timer, and optionally a second general purpose timer in that
order.
ARM: msm: Add DT support to msm_timer Add support to setup the MSM timer via information obtained from the devicetree. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> [davidb@codeaurora.org: Remove leading zeros] Signed-off-by: David Brown <davidb@codeaurora.org>
2012-09-05 12:28:53 -07:00
ARM: msm: Rework timer binding to be more general The msm timer binding I wrote is bad. First off, the clock frequency in the binding for the dgt is wrong. Software divides down the input rate by 4 to achieve the rate listed in the binding. We also treat each individual timer as a separate hardware component, when in reality there is one timer block (that may be duplicated per cpu) with multiple timers within it. Depending on the version of the hardware there can be one or two general purpose timers, status and divider control registers, and an entirely different register layout. In the next patch we'll need to know about the different register layouts so that we can properly check the status register after clearing the count. The current binding makes this complicated because the general purpose timer's reg property doesn't indicate where that status register is, and in fact it is beyond the size of the reg property. Clean all this up by just having one node for the timer hardware, and describe all the interrupts and clock frequencies supported while having one reg property that covers the entire timer register region. We'll use the compatible field in the future to determine different register layouts and if we should read the status registers, etc. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: David Brown <davidb@codeaurora.org>
2013-03-14 20:31:38 -07:00
- reg : Specifies the base address of the timer registers.
- clock-frequency : The frequency of the debug timer and the general purpose
timer(s) in Hz in that order.
ARM: msm: Add DT support to msm_timer Add support to setup the MSM timer via information obtained from the devicetree. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> [davidb@codeaurora.org: Remove leading zeros] Signed-off-by: David Brown <davidb@codeaurora.org>
2012-09-05 12:28:53 -07:00
Optional:
- cpu-offset : per-cpu offset used when the timer is accessed without the
ARM: msm: Rework timer binding to be more general The msm timer binding I wrote is bad. First off, the clock frequency in the binding for the dgt is wrong. Software divides down the input rate by 4 to achieve the rate listed in the binding. We also treat each individual timer as a separate hardware component, when in reality there is one timer block (that may be duplicated per cpu) with multiple timers within it. Depending on the version of the hardware there can be one or two general purpose timers, status and divider control registers, and an entirely different register layout. In the next patch we'll need to know about the different register layouts so that we can properly check the status register after clearing the count. The current binding makes this complicated because the general purpose timer's reg property doesn't indicate where that status register is, and in fact it is beyond the size of the reg property. Clean all this up by just having one node for the timer hardware, and describe all the interrupts and clock frequencies supported while having one reg property that covers the entire timer register region. We'll use the compatible field in the future to determine different register layouts and if we should read the status registers, etc. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: David Brown <davidb@codeaurora.org>
2013-03-14 20:31:38 -07:00
CPU remapping facilities. The offset is
cpu-offset + (0x10000 * cpu-nr).
ARM: msm: Add DT support to msm_timer Add support to setup the MSM timer via information obtained from the devicetree. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> [davidb@codeaurora.org: Remove leading zeros] Signed-off-by: David Brown <davidb@codeaurora.org>
2012-09-05 12:28:53 -07:00
Example:
ARM: msm: Rework timer binding to be more general The msm timer binding I wrote is bad. First off, the clock frequency in the binding for the dgt is wrong. Software divides down the input rate by 4 to achieve the rate listed in the binding. We also treat each individual timer as a separate hardware component, when in reality there is one timer block (that may be duplicated per cpu) with multiple timers within it. Depending on the version of the hardware there can be one or two general purpose timers, status and divider control registers, and an entirely different register layout. In the next patch we'll need to know about the different register layouts so that we can properly check the status register after clearing the count. The current binding makes this complicated because the general purpose timer's reg property doesn't indicate where that status register is, and in fact it is beyond the size of the reg property. Clean all this up by just having one node for the timer hardware, and describe all the interrupts and clock frequencies supported while having one reg property that covers the entire timer register region. We'll use the compatible field in the future to determine different register layouts and if we should read the status registers, etc. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: David Brown <davidb@codeaurora.org>
2013-03-14 20:31:38 -07:00
timer@200a000 {
compatible = "qcom,scss-timer", "qcom,msm-timer";
interrupts = <1 1 0x301>,
<1 2 0x301>,
<1 3 0x301>;
reg = <0x0200a000 0x100>;
clock-frequency = <19200000>,
<32768>;
ARM: msm: Add DT support to msm_timer Add support to setup the MSM timer via information obtained from the devicetree. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> [davidb@codeaurora.org: Remove leading zeros] Signed-off-by: David Brown <davidb@codeaurora.org>
2012-09-05 12:28:53 -07:00
cpu-offset = <0x40000>;
};
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