125 lines
3 KiB
C
125 lines
3 KiB
C
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#define R100_TRACK_MAX_TEXTURE 3
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#define R200_TRACK_MAX_TEXTURE 6
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#define R300_TRACK_MAX_TEXTURE 16
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#define R100_MAX_CB 1
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#define R300_MAX_CB 4
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/*
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* CS functions
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*/
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struct r100_cs_track_cb {
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struct radeon_object *robj;
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unsigned pitch;
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unsigned cpp;
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unsigned offset;
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};
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struct r100_cs_track_array {
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struct radeon_object *robj;
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unsigned esize;
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};
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struct r100_cs_cube_info {
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struct radeon_object *robj;
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unsigned offset;
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unsigned width;
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unsigned height;
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};
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struct r100_cs_track_texture {
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struct radeon_object *robj;
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struct r100_cs_cube_info cube_info[5]; /* info for 5 non-primary faces */
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unsigned pitch;
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unsigned width;
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unsigned height;
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unsigned num_levels;
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unsigned cpp;
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unsigned tex_coord_type;
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unsigned txdepth;
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unsigned width_11;
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unsigned height_11;
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bool use_pitch;
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bool enabled;
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bool roundup_w;
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bool roundup_h;
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};
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struct r100_cs_track_limits {
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unsigned num_cb;
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unsigned num_texture;
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unsigned max_levels;
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};
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struct r100_cs_track {
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struct radeon_device *rdev;
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unsigned num_cb;
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unsigned num_texture;
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unsigned maxy;
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unsigned vtx_size;
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unsigned vap_vf_cntl;
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unsigned immd_dwords;
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unsigned num_arrays;
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unsigned max_indx;
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struct r100_cs_track_array arrays[11];
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struct r100_cs_track_cb cb[R300_MAX_CB];
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struct r100_cs_track_cb zb;
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struct r100_cs_track_texture textures[R300_TRACK_MAX_TEXTURE];
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bool z_enabled;
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bool separate_cube;
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};
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int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track);
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void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track);
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int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
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struct radeon_cs_reloc **cs_reloc);
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void r100_cs_dump_packet(struct radeon_cs_parser *p,
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struct radeon_cs_packet *pkt);
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int r100_cs_packet_parse_vline(struct radeon_cs_parser *p);
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int r200_packet0_check(struct radeon_cs_parser *p,
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struct radeon_cs_packet *pkt,
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unsigned idx, unsigned reg);
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static inline int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
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struct radeon_cs_packet *pkt,
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unsigned idx,
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unsigned reg)
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{
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int r;
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u32 tile_flags = 0;
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u32 tmp;
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struct radeon_cs_reloc *reloc;
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struct radeon_cs_chunk *ib_chunk;
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ib_chunk = &p->chunks[p->chunk_ib_idx];
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r = r100_cs_packet_next_reloc(p, &reloc);
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if (r) {
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DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
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idx, reg);
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r100_cs_dump_packet(p, pkt);
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return r;
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}
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tmp = ib_chunk->kdata[idx] & 0x003fffff;
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tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
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if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
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tile_flags |= RADEON_DST_TILE_MACRO;
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if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
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if (reg == RADEON_SRC_PITCH_OFFSET) {
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DRM_ERROR("Cannot src blit from microtiled surface\n");
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r100_cs_dump_packet(p, pkt);
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return -EINVAL;
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}
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tile_flags |= RADEON_DST_TILE_MICRO;
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}
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tmp |= tile_flags;
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p->ib->ptr[idx] = (ib_chunk->kdata[idx] & 0x3fc00000) | tmp;
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return 0;
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}
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