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linux-pinenote/arch/arm/include/asm/hardware/gic.h

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[ARM] Add support for ARM GIC Add support for the ARM Generic Interrupt Controller. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-08-18 21:31:00 +01:00
/*
[ARM] move include/asm-arm to arch/arm/include/asm Move platform independent header files to arch/arm/include/asm, leaving those in asm/arch* and asm/plat* alone. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-08-02 10:55:55 +01:00
* arch/arm/include/asm/hardware/gic.h
[ARM] Add support for ARM GIC Add support for the ARM Generic Interrupt Controller. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-08-18 21:31:00 +01:00
*
* Copyright (C) 2002 ARM Limited, All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARM_HARDWARE_GIC_H
#define __ASM_ARM_HARDWARE_GIC_H
#include <linux/compiler.h>
#define GIC_CPU_CTRL 0x00
#define GIC_CPU_PRIMASK 0x04
#define GIC_CPU_BINPOINT 0x08
#define GIC_CPU_INTACK 0x0c
#define GIC_CPU_EOI 0x10
#define GIC_CPU_RUNNINGPRI 0x14
#define GIC_CPU_HIGHPRI 0x18
#define GIC_DIST_CTRL 0x000
#define GIC_DIST_CTR 0x004
#define GIC_DIST_ENABLE_SET 0x100
#define GIC_DIST_ENABLE_CLEAR 0x180
#define GIC_DIST_PENDING_SET 0x200
#define GIC_DIST_PENDING_CLEAR 0x280
#define GIC_DIST_ACTIVE_BIT 0x300
#define GIC_DIST_PRI 0x400
#define GIC_DIST_TARGET 0x800
#define GIC_DIST_CONFIG 0xc00
#define GIC_DIST_SOFTINT 0xf00
#ifndef __ASSEMBLY__
ARM: gic: add irq_domain support Convert the gic interrupt controller to use irq domains in preparation for device-tree binding and MULTI_IRQ. This allows for translation between GIC interrupt IDs and Linux irq numbers. The meaning of irq_offset has changed. It now is just the number of skipped GIC interrupt IDs for the controller. It will be 16 for primary GIC and 32 for secondary GICs. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Reviewed-by: Jamie Iles <jamie@jamieiles.com> Tested-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Grant Likely <grant.likely@secretlab.ca>
2011-09-28 21:25:31 -05:00
#include <linux/irqdomain.h>
struct device_node;
ARM: 6777/1: gic: Add hooks for architecture specific extensions Few architectures combine the GIC with an external interrupt controller. On such systems it may be necessary to update both the GIC registers and the external controller's registers to control IRQ behavior. This can be addressed in couple of possible methods. 1. Export common GIC routines along with 'struct irq_chip gic_chip' and allow architectures to have custom function by override. 2. Provide architecture specific function pointer hooks within GIC library and leave platforms to add the necessary code as part of these hooks. First one might be non-intrusive but have few shortcomings like arch needs to have there own custom gic library. Locks used should be common since it caters to same IRQs etc. Maintenance point of view also it leads to multiple file fixes. The second probably is cleaner and portable. It ensures that all the common GIC infrastructure is not touched and also provides archs to address their specific issue. Cc: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Colin Cross <ccross@android.com> Tested-by: Colin Cross <ccross@android.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-03-02 08:03:22 +01:00
extern struct irq_chip gic_arch_extn;
ARM: GIC: consolidate gic_cpu_base_addr to common GIC code Every architecture using the GIC has a gic_cpu_base_addr pointer for GIC 0 for their entry assembly code to use to decode the cause of the current interrupt. Move this into the common GIC code. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-12-04 16:13:29 +00:00
ARM: gic: allow GIC to support non-banked setups The GIC support code is heavily using the fact that hardware implementations are exposing banked registers. Unfortunately, it looks like at least one GIC implementation (EXYNOS) offers both the distributor and the CPU interfaces at different addresses, depending on the CPU. This problem is solved by allowing the distributor and CPU interface addresses to be per-cpu variables for the platforms that require it. The EXYNOS code is updated not to mess with the GIC internals while handling interrupts, and struct gic_chip_data is back to being private. The DT binding for the gic is updated to allow an optional "cpu-offset" value, which is used to compute the various base addresses. Finally, a new config option (GIC_NON_BANKED) is used to control this feature, so the overhead is only present on kernels compiled with support for EXYNOS. Tested on Origen (EXYNOS4) and Panda (OMAP4). Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2011-11-12 16:09:49 +00:00
void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *,
u32 offset);
ARM: gic: add OF based initialization This adds ARM gic interrupt controller initialization using device tree data. The initialization function is intended to be called by of_irq_init function like this: const static struct of_device_id irq_match[] = { { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, }, {} }; static void __init init_irqs(void) { of_irq_init(irq_match); } Signed-off-by: Rob Herring <rob.herring@calxeda.com> Reviewed-by: Jamie Iles <jamie@jamieiles.com> Tested-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Grant Likely <grant.likely@secretlab.ca>
2011-09-28 21:27:52 -05:00
int gic_of_init(struct device_node *node, struct device_node *parent);
ARM: GIC: Remove MMIO address from gic_cpu_init, rename to gic_secondary_init We don't need to re-pass the base address for the CPU interfaces to the GIC for secondary CPUs, as it will never be different from the boot CPU - and even if it was, we'd overwrite the boot CPU's base address. Get rid of this argument, and rename to gic_secondary_init(). Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-12-04 16:01:03 +00:00
void gic_secondary_init(unsigned int);
ARM: GIC: Add global gic_handle_irq() function Provide the GIC code with a low level handler that can be used by platforms using CONFIG_MULTI_IRQ_HANDLER. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2011-09-06 09:56:17 +01:00
void gic_handle_irq(struct pt_regs *regs);
[ARM] 4108/2: Allow multiple GIC interrupt controllers in a system The current implementation only assumes one GIC to be present in the system. However, there are platforms with more than one cascaded interrupt controllers (RealView/EB MPCore for example). Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-02-14 19:14:56 +01:00
void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
[ARM] smp: fix cpumask usage in ARM SMP code The ARM SMP code wasn't properly updated for the cpumask changes, which results in smp_timer_broadcast() broadcasting ticks to non-online CPUs. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-05-17 16:20:18 +01:00
void gic_raise_softirq(const struct cpumask *mask, unsigned int irq);
ARM: GIC: move gic_chip_data structure declaration to header Since Samsung EXYNOS4210 cannot support register banking in GIC, so needs to update CPU interface base address. The 'gic_chip_data' is used for it, this patch moves gic_chip_data structure declaraton to arch/arm/include/asm/hardware/gic.h to use it. Cc: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Changhwan Youn <chaos.youn@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2011-07-16 10:49:47 +09:00
ARM: gic: allow GIC to support non-banked setups The GIC support code is heavily using the fact that hardware implementations are exposing banked registers. Unfortunately, it looks like at least one GIC implementation (EXYNOS) offers both the distributor and the CPU interfaces at different addresses, depending on the CPU. This problem is solved by allowing the distributor and CPU interface addresses to be per-cpu variables for the platforms that require it. The EXYNOS code is updated not to mess with the GIC internals while handling interrupts, and struct gic_chip_data is back to being private. The DT binding for the gic is updated to allow an optional "cpu-offset" value, which is used to compute the various base addresses. Finally, a new config option (GIC_NON_BANKED) is used to control this feature, so the overhead is only present on kernels compiled with support for EXYNOS. Tested on Origen (EXYNOS4) and Panda (OMAP4). Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2011-11-12 16:09:49 +00:00
static inline void gic_init(unsigned int nr, int start,
void __iomem *dist , void __iomem *cpu)
{
gic_init_bases(nr, start, dist, cpu, 0);
}
[ARM] Add support for ARM GIC Add support for the ARM Generic Interrupt Controller. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-08-18 21:31:00 +01:00
#endif
#endif
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