forge/glider
1
0
Fork 0
mirror of https://gitlab.com/zephray/glider.git synced 2024-12-22 21:51:47 +00:00
Code Issues 1 Projects Releases Packages Wiki Activity Actions
glider/pcb/mainboard/pcb.kicad_pro
Wenting Zhang d6f6bd5514 pcb: r0p6
2023-06-25 22:37:15 -04:00

1178 lines
26 KiB
Text
Executable file
Raw Blame History

{
"board": {
"3dviewports": [],
"design_settings": {
"defaults": {
"board_outline_line_width": 0.049999999999999996,
"copper_line_width": 0.19999999999999998,
"copper_text_italic": false,
"copper_text_size_h": 1.5,
"copper_text_size_v": 1.5,
"copper_text_thickness": 0.3,
"copper_text_upright": false,
"courtyard_line_width": 0.049999999999999996,
"dimension_precision": 4,
"dimension_units": 3,
"dimensions": {
"arrow_length": 1270000,
"extension_offset": 500000,
"keep_text_aligned": true,
"suppress_zeroes": false,
"text_position": 0,
"units_format": 1
},
"fab_line_width": 0.09999999999999999,
"fab_text_italic": false,
"fab_text_size_h": 1.0,
"fab_text_size_v": 1.0,
"fab_text_thickness": 0.15,
"fab_text_upright": false,
"other_line_width": 0.09999999999999999,
"other_text_italic": false,
"other_text_size_h": 1.0,
"other_text_size_v": 1.0,
"other_text_thickness": 0.15,
"other_text_upright": false,
"pads": {
"drill": 0.762,
"height": 1.524,
"width": 1.524
},
"silk_line_width": 0.12,
"silk_text_italic": false,
"silk_text_size_h": 0.7,
"silk_text_size_v": 0.7,
"silk_text_thickness": 0.09999999999999999,
"silk_text_upright": false,
"zones": {
"45_degree_only": false,
"min_clearance": 0.11
}
},
"diff_pair_dimensions": [
{
"gap": 0.0,
"via_gap": 0.0,
"width": 0.0
}
],
"drc_exclusions": [],
"meta": {
"version": 2
},
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"connection_width": "warning",
"copper_edge_clearance": "error",
"copper_sliver": "warning",
"courtyards_overlap": "warning",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"footprint": "error",
"footprint_type_mismatch": "error",
"hole_clearance": "error",
"hole_near_hole": "error",
"invalid_outline": "error",
"isolated_copper": "warning",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"length_out_of_range": "error",
"lib_footprint_issues": "warning",
"lib_footprint_mismatch": "warning",
"malformed_courtyard": "error",
"microvia_drill_out_of_range": "error",
"missing_courtyard": "ignore",
"missing_footprint": "warning",
"net_conflict": "warning",
"npth_inside_courtyard": "ignore",
"padstack": "error",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
"silk_edge_clearance": "warning",
"silk_over_copper": "error",
"silk_overlap": "error",
"skew_out_of_range": "error",
"solder_mask_bridge": "error",
"starved_thermal": "error",
"text_height": "warning",
"text_thickness": "warning",
"through_hole_pad_without_hole": "error",
"too_many_vias": "error",
"track_dangling": "warning",
"track_width": "error",
"tracks_crossing": "error",
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "warning",
"zones_intersect": "error"
},
"rules": {
"allow_blind_buried_vias": false,
"allow_microvias": false,
"max_error": 0.005,
"min_clearance": 0.0,
"min_connection": 0.0,
"min_copper_edge_clearance": 0.024999999999999998,
"min_hole_clearance": 0.0,
"min_hole_to_hole": 0.25,
"min_microvia_diameter": 0.19999999999999998,
"min_microvia_drill": 0.09999999999999999,
"min_resolved_spokes": 2,
"min_silk_clearance": 0.0,
"min_text_height": 0.7,
"min_text_thickness": 0.08,
"min_through_hole_diameter": 0.19999999999999998,
"min_track_width": 0.09999999999999999,
"min_via_annular_width": 0.049999999999999996,
"min_via_diameter": 0.44999999999999996,
"solder_mask_clearance": 0.0,
"solder_mask_min_width": 0.0,
"solder_mask_to_copper_clearance": 0.0,
"use_height_for_length_calcs": true
},
"teardrop_options": [
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 5,
"td_on_pad_in_zone": false,
"td_onpadsmd": true,
"td_onroundshapesonly": false,
"td_ontrackend": false,
"td_onviapad": true
}
],
"teardrop_parameters": [
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_round_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_rect_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_track_end",
"td_width_to_size_filter_ratio": 0.9
}
],
"track_widths": [
0.0,
0.1,
0.11,
0.12,
0.13,
0.15,
0.2,
0.3,
0.5,
0.6,
1.0
],
"via_dimensions": [
{
"diameter": 0.0,
"drill": 0.0
},
{
"diameter": 0.46,
"drill": 0.2
}
],
"zones_allow_external_fillets": false,
"zones_use_no_outline": true
},
"layer_presets": [],
"viewports": []
},
"boards": [],
"cvpcb": {
"equivalence_files": []
},
"erc": {
"erc_exclusions": [],
"meta": {
"version": 0
},
"pin_map": [
[
0,
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
2,
0,
1,
0,
0,
1,
0,
2,
2,
2,
2
],
[
0,
0,
0,
0,
0,
0,
1,
0,
1,
0,
1,
2
],
[
0,
1,
0,
0,
0,
0,
1,
1,
2,
1,
1,
2
],
[
0,
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
2
],
[
1,
1,
1,
1,
1,
0,
1,
1,
1,
1,
1,
2
],
[
0,
0,
0,
1,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
2,
1,
2,
0,
0,
1,
0,
2,
2,
2,
2
],
[
0,
2,
0,
1,
0,
0,
1,
0,
2,
0,
0,
2
],
[
0,
2,
1,
1,
0,
0,
1,
0,
2,
0,
0,
2
],
[
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2
]
],
"rule_severities": {
"bus_definition_conflict": "error",
"bus_entry_needed": "error",
"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"conflicting_netclasses": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_reference": "error",
"duplicate_sheet_names": "error",
"endpoint_off_grid": "warning",
"extra_units": "error",
"global_label_dangling": "warning",
"hier_label_mismatch": "error",
"label_dangling": "error",
"lib_symbol_issues": "warning",
"missing_bidi_pin": "warning",
"missing_input_pin": "warning",
"missing_power_pin": "error",
"missing_unit": "warning",
"multiple_net_names": "warning",
"net_not_bus_member": "warning",
"no_connect_connected": "warning",
"no_connect_dangling": "warning",
"pin_not_connected": "error",
"pin_not_driven": "error",
"pin_to_pin": "warning",
"power_pin_not_driven": "error",
"similar_labels": "warning",
"simulation_model_issue": "error",
"unannotated": "error",
"unit_value_mismatch": "error",
"unresolved_variable": "error",
"wire_dangling": "error"
}
},
"libraries": {
"pinned_footprint_libs": [],
"pinned_symbol_libs": []
},
"meta": {
"filename": "pcb.kicad_pro",
"version": 1
},
"net_settings": {
"classes": [
{
"bus_width": 12,
"clearance": 0.11,
"diff_pair_gap": 0.1,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.11,
"via_diameter": 0.45,
"via_drill": 0.2,
"wire_width": 6
},
{
"bus_width": 12,
"clearance": 0.11,
"diff_pair_gap": 0.11,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.15,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "DP",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.15,
"via_diameter": 0.45,
"via_drill": 0.2,
"wire_width": 6
},
{
"bus_width": 12,
"clearance": 0.11,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "EPD",
"pcb_color": "rgb(255, 0, 191)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.11,
"via_diameter": 0.45,
"via_drill": 0.2,
"wire_width": 6
},
{
"bus_width": 12,
"clearance": 0.11,
"diff_pair_gap": 0.11,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.15,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "LVDS",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.15,
"via_diameter": 0.45,
"via_drill": 0.2,
"wire_width": 6
},
{
"bus_width": 12,
"clearance": 0.1,
"diff_pair_gap": 0.1,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.1,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "SDRAM_A",
"pcb_color": "rgb(103, 255, 0)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.1,
"via_diameter": 0.45,
"via_drill": 0.2,
"wire_width": 6
},
{
"bus_width": 12,
"clearance": 0.1,
"diff_pair_gap": 0.1,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.1,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "SDRAM_H",
"pcb_color": "rgb(255, 252, 0)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.1,
"via_diameter": 0.45,
"via_drill": 0.2,
"wire_width": 6
},
{
"bus_width": 12,
"clearance": 0.1,
"diff_pair_gap": 0.1,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.1,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "SDRAM_L",
"pcb_color": "rgb(255, 131, 3)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.1,
"via_diameter": 0.45,
"via_drill": 0.2,
"wire_width": 6
},
{
"bus_width": 12,
"clearance": 0.11,
"diff_pair_gap": 0.11,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.18,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "USB",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.15,
"via_diameter": 0.45,
"via_drill": 0.2,
"wire_width": 6
}
],
"meta": {
"version": 3
},
"net_colors": {
"+1V1": "rgb(255, 92, 56)",
"+1V35": "rgb(185, 61, 143)",
"+3V3": "rgb(179, 228, 50)",
"+5V": "rgb(255, 122, 107)",
"GND": "rgb(0, 94, 255)"
},
"netclass_assignments": null,
"netclass_patterns": [
{
"netclass": "DP",
"pattern": "/dp_in/DP0N"
},
{
"netclass": "DP",
"pattern": "/dp_in/DP0P"
},
{
"netclass": "DP",
"pattern": "/dp_in/DP1N"
},
{
"netclass": "DP",
"pattern": "/dp_in/DP1P"
},
{
"netclass": "DP",
"pattern": "/dp_in/DPAUXN"
},
{
"netclass": "DP",
"pattern": "/dp_in/DPAUXP"
},
{
"netclass": "DP",
"pattern": "/dp_in/RX1N"
},
{
"netclass": "DP",
"pattern": "/dp_in/RX1NC"
},
{
"netclass": "DP",
"pattern": "/dp_in/RX1P"
},
{
"netclass": "DP",
"pattern": "/dp_in/RX1PC"
},
{
"netclass": "DP",
"pattern": "/dp_in/RX2N"
},
{
"netclass": "DP",
"pattern": "/dp_in/RX2NC"
},
{
"netclass": "DP",
"pattern": "/dp_in/RX2P"
},
{
"netclass": "DP",
"pattern": "/dp_in/RX2PC"
},
{
"netclass": "DP",
"pattern": "/dp_in/TX1N"
},
{
"netclass": "DP",
"pattern": "/dp_in/TX1NC"
},
{
"netclass": "DP",
"pattern": "/dp_in/TX1P"
},
{
"netclass": "DP",
"pattern": "/dp_in/TX1PC"
},
{
"netclass": "DP",
"pattern": "/dp_in/TX2N"
},
{
"netclass": "DP",
"pattern": "/dp_in/TX2NC"
},
{
"netclass": "DP",
"pattern": "/dp_in/TX2P"
},
{
"netclass": "DP",
"pattern": "/dp_in/TX2PC"
},
{
"netclass": "EPD",
"pattern": "/eink/ED0"
},
{
"netclass": "EPD",
"pattern": "/eink/ED1"
},
{
"netclass": "EPD",
"pattern": "/eink/ED10"
},
{
"netclass": "EPD",
"pattern": "/eink/ED11"
},
{
"netclass": "EPD",
"pattern": "/eink/ED12"
},
{
"netclass": "EPD",
"pattern": "/eink/ED13"
},
{
"netclass": "EPD",
"pattern": "/eink/ED14"
},
{
"netclass": "EPD",
"pattern": "/eink/ED15"
},
{
"netclass": "EPD",
"pattern": "/eink/ED2"
},
{
"netclass": "EPD",
"pattern": "/eink/ED3"
},
{
"netclass": "EPD",
"pattern": "/eink/ED4"
},
{
"netclass": "EPD",
"pattern": "/eink/ED5"
},
{
"netclass": "EPD",
"pattern": "/eink/ED6"
},
{
"netclass": "EPD",
"pattern": "/eink/ED7"
},
{
"netclass": "EPD",
"pattern": "/eink/ED8"
},
{
"netclass": "EPD",
"pattern": "/eink/ED9"
},
{
"netclass": "EPD",
"pattern": "/eink/ESDCLK"
},
{
"netclass": "EPD",
"pattern": "/eink/ESDLE"
},
{
"netclass": "EPD",
"pattern": "/eink/ESDOE"
},
{
"netclass": "EPD",
"pattern": "EPDC_D0"
},
{
"netclass": "EPD",
"pattern": "EPDC_D1"
},
{
"netclass": "EPD",
"pattern": "EPDC_D10"
},
{
"netclass": "EPD",
"pattern": "EPDC_D11"
},
{
"netclass": "EPD",
"pattern": "EPDC_D12"
},
{
"netclass": "EPD",
"pattern": "EPDC_D13"
},
{
"netclass": "EPD",
"pattern": "EPDC_D14"
},
{
"netclass": "EPD",
"pattern": "EPDC_D15"
},
{
"netclass": "EPD",
"pattern": "EPDC_D2"
},
{
"netclass": "EPD",
"pattern": "EPDC_D3"
},
{
"netclass": "EPD",
"pattern": "EPDC_D4"
},
{
"netclass": "EPD",
"pattern": "EPDC_D5"
},
{
"netclass": "EPD",
"pattern": "EPDC_D6"
},
{
"netclass": "EPD",
"pattern": "EPDC_D7"
},
{
"netclass": "EPD",
"pattern": "EPDC_D8"
},
{
"netclass": "EPD",
"pattern": "EPDC_D9"
},
{
"netclass": "EPD",
"pattern": "EPDC_GDCLK"
},
{
"netclass": "EPD",
"pattern": "EPDC_GDOE"
},
{
"netclass": "EPD",
"pattern": "EPDC_GDSP"
},
{
"netclass": "EPD",
"pattern": "EPDC_SDCE0"
},
{
"netclass": "EPD",
"pattern": "EPDC_SDCLK"
},
{
"netclass": "EPD",
"pattern": "EPDC_SDLE"
},
{
"netclass": "EPD",
"pattern": "EPDC_SDOE"
},
{
"netclass": "LVDS",
"pattern": "LVDS_EVEN_AN"
},
{
"netclass": "LVDS",
"pattern": "LVDS_EVEN_AP"
},
{
"netclass": "LVDS",
"pattern": "LVDS_EVEN_BN"
},
{
"netclass": "LVDS",
"pattern": "LVDS_EVEN_BP"
},
{
"netclass": "LVDS",
"pattern": "LVDS_EVEN_CN"
},
{
"netclass": "LVDS",
"pattern": "LVDS_EVEN_CP"
},
{
"netclass": "LVDS",
"pattern": "LVDS_ODD_AN"
},
{
"netclass": "LVDS",
"pattern": "LVDS_ODD_AP"
},
{
"netclass": "LVDS",
"pattern": "LVDS_ODD_BN"
},
{
"netclass": "LVDS",
"pattern": "LVDS_ODD_BP"
},
{
"netclass": "LVDS",
"pattern": "LVDS_ODD_CKN"
},
{
"netclass": "LVDS",
"pattern": "LVDS_ODD_CKP"
},
{
"netclass": "LVDS",
"pattern": "LVDS_ODD_CN"
},
{
"netclass": "LVDS",
"pattern": "LVDS_ODD_CP"
},
{
"netclass": "SDRAM_A",
"pattern": "/fpga_ddr/DRAM_ADDR0"
},
{
"netclass": "SDRAM_A",
"pattern": "/fpga_ddr/DRAM_ADDR1"
},
{
"netclass": "SDRAM_A",
"pattern": "/fpga_ddr/DRAM_ADDR10"
},
{
"netclass": "SDRAM_A",
"pattern": "/fpga_ddr/DRAM_ADDR11"
},
{
"netclass": "SDRAM_A",
"pattern": "/fpga_ddr/DRAM_ADDR12"
},
{
"netclass": "SDRAM_A",
"pattern": "/fpga_ddr/DRAM_ADDR13"
},
{
"netclass": "SDRAM_A",
"pattern": "/fpga_ddr/DRAM_ADDR14"
},
{
"netclass": "SDRAM_A",
"pattern": "/fpga_ddr/DRAM_ADDR2"
},
{
"netclass": "SDRAM_A",
"pattern": "/fpga_ddr/DRAM_ADDR3"
},
{
"netclass": "SDRAM_A",
"pattern": "/fpga_ddr/DRAM_ADDR4"
},
{
"netclass": "SDRAM_A",
"pattern": "/fpga_ddr/DRAM_ADDR5"
},
{
"netclass": "SDRAM_A",
"pattern": "/fpga_ddr/DRAM_ADDR6"
},
{
"netclass": "SDRAM_A",
"pattern": "/fpga_ddr/DRAM_ADDR7"
},
{
"netclass": "SDRAM_A",
"pattern": "/fpga_ddr/DRAM_ADDR8"
},
{
"netclass": "SDRAM_A",
"pattern": "/fpga_ddr/DRAM_ADDR9"
},
{
"netclass": "SDRAM_A",
"pattern": "/fpga_ddr/DRAM_BA0"
},
{
"netclass": "SDRAM_A",
"pattern": "/fpga_ddr/DRAM_BA1"
},
{
"netclass": "SDRAM_A",
"pattern": "/fpga_ddr/DRAM_BA2"
},
{
"netclass": "SDRAM_A",
"pattern": "/fpga_ddr/DRAM_CASB"
},
{
"netclass": "SDRAM_A",
"pattern": "/fpga_ddr/DRAM_CKE"
},
{
"netclass": "SDRAM_A",
"pattern": "/fpga_ddr/DRAM_CKN"
},
{
"netclass": "SDRAM_A",
"pattern": "/fpga_ddr/DRAM_CKP"
},
{
"netclass": "SDRAM_A",
"pattern": "/fpga_ddr/DRAM_CSB"
},
{
"netclass": "SDRAM_A",
"pattern": "/fpga_ddr/DRAM_ODT"
},
{
"netclass": "SDRAM_A",
"pattern": "/fpga_ddr/DRAM_RASB"
},
{
"netclass": "SDRAM_A",
"pattern": "/fpga_ddr/DRAM_RST"
},
{
"netclass": "SDRAM_A",
"pattern": "/fpga_ddr/DRAM_WEB"
},
{
"netclass": "SDRAM_H",
"pattern": "/fpga_ddr/DRAM_DATA10"
},
{
"netclass": "SDRAM_H",
"pattern": "/fpga_ddr/DRAM_DATA11"
},
{
"netclass": "SDRAM_H",
"pattern": "/fpga_ddr/DRAM_DATA12"
},
{
"netclass": "SDRAM_H",
"pattern": "/fpga_ddr/DRAM_DATA13"
},
{
"netclass": "SDRAM_H",
"pattern": "/fpga_ddr/DRAM_DATA14"
},
{
"netclass": "SDRAM_H",
"pattern": "/fpga_ddr/DRAM_DATA15"
},
{
"netclass": "SDRAM_H",
"pattern": "/fpga_ddr/DRAM_DATA8"
},
{
"netclass": "SDRAM_H",
"pattern": "/fpga_ddr/DRAM_DATA9"
},
{
"netclass": "SDRAM_H",
"pattern": "/fpga_ddr/DRAM_UDM"
},
{
"netclass": "SDRAM_H",
"pattern": "/fpga_ddr/DRAM_UDQSN"
},
{
"netclass": "SDRAM_H",
"pattern": "/fpga_ddr/DRAM_UDQSP"
},
{
"netclass": "SDRAM_L",
"pattern": "/fpga_ddr/DRAM_DATA0"
},
{
"netclass": "SDRAM_L",
"pattern": "/fpga_ddr/DRAM_DATA1"
},
{
"netclass": "SDRAM_L",
"pattern": "/fpga_ddr/DRAM_DATA2"
},
{
"netclass": "SDRAM_L",
"pattern": "/fpga_ddr/DRAM_DATA3"
},
{
"netclass": "SDRAM_L",
"pattern": "/fpga_ddr/DRAM_DATA4"
},
{
"netclass": "SDRAM_L",
"pattern": "/fpga_ddr/DRAM_DATA5"
},
{
"netclass": "SDRAM_L",
"pattern": "/fpga_ddr/DRAM_DATA6"
},
{
"netclass": "SDRAM_L",
"pattern": "/fpga_ddr/DRAM_DATA7"
},
{
"netclass": "SDRAM_L",
"pattern": "/fpga_ddr/DRAM_LDM"
},
{
"netclass": "SDRAM_L",
"pattern": "/fpga_ddr/DRAM_LDQSN"
},
{
"netclass": "SDRAM_L",
"pattern": "/fpga_ddr/DRAM_LDQSP"
}
]
},
"pcbnew": {
"last_paths": {
"gencad": "",
"idf": "",
"netlist": "",
"specctra_dsn": "",
"step": "",
"vrml": ""
},
"page_layout_descr_file": ""
},
"schematic": {
"annotate_start_num": 400,
"drawing": {
"dashed_lines_dash_length_ratio": 12.0,
"dashed_lines_gap_length_ratio": 3.0,
"default_bus_thickness": 12.0,
"default_line_thickness": 6.0,
"default_text_size": 50.0,
"default_wire_thickness": 6.0,
"field_names": [],
"intersheets_ref_own_page": false,
"intersheets_ref_prefix": "",
"intersheets_ref_short": false,
"intersheets_ref_show": false,
"intersheets_ref_suffix": "",
"junction_size_choice": 3,
"label_size_ratio": 0.375,
"pin_symbol_size": 25.0,
"text_offset_ratio": 0.15
},
"legacy_lib_dir": "",
"legacy_lib_list": [],
"meta": {
"version": 1
},
"net_format_name": "",
"ngspice": {
"fix_include_paths": true,
"fix_passive_vals": false,
"meta": {
"version": 0
},
"model_mode": 0,
"workbook_filename": ""
},
"page_layout_descr_file": "",
"plot_directory": "./",
"spice_adjust_passive_values": false,
"spice_current_sheet_as_root": false,
"spice_external_command": "spice \"%I\"",
"spice_model_current_sheet_as_root": true,
"spice_save_all_currents": false,
"spice_save_all_voltages": false,
"subpart_first_id": 65,
"subpart_id_separator": 0
},
"sheets": [
[
"4654897e-3e2f-4522-96c3-20b19803c088",
""
],
[
"0606a719-6980-4867-837f-aa642737d361",
"power"
],
[
"35d2a4e1-1cb2-4b6c-a7fb-e3a9449d4ff3",
"fpga"
],
[
"b1d5941d-0481-47a2-a434-0b8e587a166a",
"eink"
],
[
"866a5b4a-453a-413a-94a2-5e610f40d8dd",
"fpga_ddr"
],
[
"80373716-d41f-4f06-92dd-577434075703",
"dp_in"
],
[
"f69cfcc8-f979-4315-84ee-316a84fb66a2",
"mcu"
]
],
"text_variables": {}
}
Reference in a new issue View git blame Copy permalink