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r0p7 wip, check in before switch to kicad 8
This commit is contained in:
Wenting Zhang
parent
37f15e93d3
commit
d99766b0b7
19 changed files with 155305 additions and 46805 deletions
22
CHANGES.txt
22
CHANGES.txt
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@ -10,3 +10,25 @@ R0.3
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1. Remove on-board 39pin/ 50pin connector, switch to 40pin connector or EPD
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1. Remove on-board 39pin/ 50pin connector, switch to 40pin connector or EPD
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2. Remove DSI input connector
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2. Remove DSI input connector
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3. Add DisplayPort to LVDS bridge chip and DisplayPort input
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3. Add DisplayPort to LVDS bridge chip and DisplayPort input
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R0.4
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1. Use Type-C input instead of full-size DisplayPort port
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R0.5
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1. Switch from MAX17135 PMIC to TPS65185 PMIC
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2. Switch to a different TypeC connector model
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3. Added global current limit
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R0.6
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1. Switch to individual DCDCs for Eink power supply
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Lite R0.1
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1. Use DVI TMDS input in place of Type-C input and DP bridge
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2. Use DCDC instead of charge pump + zener diode for lower Iq
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3. Add user button
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4. Add VCOM measure capability
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5. Add RP2040 SWD connector
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R0.7
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1. Import DVI TMDS input, newly revised power supply and user button from RL0.1
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2. Connect FPGA to RP2040's hardware SPI
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69085
pcb/common/footprints.pretty/10137065-00021LF.step
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69085
pcb/common/footprints.pretty/10137065-00021LF.step
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41615
pcb/common/footprints.pretty/467651301.stp
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41615
pcb/common/footprints.pretty/467651301.stp
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Load diff
429
pcb/common/footprints.pretty/AMPHENOL_10137065-00021LF.kicad_mod
Normal file
429
pcb/common/footprints.pretty/AMPHENOL_10137065-00021LF.kicad_mod
Normal file
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@ -0,0 +1,429 @@
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||||||
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(footprint "AMPHENOL_10137065-00021LF" (version 20221018) (generator pcbnew)
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(layer "F.Cu")
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(attr smd)
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(fp_text reference "REF**" (at -1.27 -9.525) (layer "F.SilkS")
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(effects (font (size 1 1) (thickness 0.15)))
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(tstamp d3be9b9e-ff7f-4bb9-8f14-e46d4012521a)
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)
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(fp_text value "AMPHENOL_10137065-00021LF" (at 11.43 -7.62) (layer "F.Fab")
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(effects (font (size 1 1) (thickness 0.15)))
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(tstamp 3633ab49-c0a2-4353-91f8-4e66a8137092)
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)
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||||||
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(fp_text user "PCB EDGE" (at 5.715 1.27) (layer "F.Fab")
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949
pcb/common/footprints.pretty/EVQP7C.step
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949
pcb/common/footprints.pretty/EVQP7C.step
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/* Generated by software containing ST-Developer
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/* name */ '/Users/wenting/Downloads/EVQP7C.step',
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#323=EDGE_CURVE('',#253,#256,#131,.T.);
|
||||||
|
#324=EDGE_CURVE('',#258,#233,#132,.T.);
|
||||||
|
#325=EDGE_CURVE('',#259,#232,#133,.T.);
|
||||||
|
#326=EDGE_CURVE('',#258,#259,#134,.T.);
|
||||||
|
#327=EDGE_CURVE('',#246,#251,#135,.T.);
|
||||||
|
#328=EDGE_CURVE('',#254,#258,#136,.T.);
|
||||||
|
#329=EDGE_CURVE('',#260,#259,#137,.T.);
|
||||||
|
#330=EDGE_CURVE('',#261,#260,#138,.T.);
|
||||||
|
#331=EDGE_CURVE('',#261,#243,#139,.T.);
|
||||||
|
#332=EDGE_CURVE('',#230,#261,#140,.T.);
|
||||||
|
#333=EDGE_CURVE('',#231,#260,#141,.T.);
|
||||||
|
#334=ORIENTED_EDGE('',*,*,#262,.F.);
|
||||||
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#335=ORIENTED_EDGE('',*,*,#263,.T.);
|
||||||
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#336=ORIENTED_EDGE('',*,*,#264,.F.);
|
||||||
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#337=ORIENTED_EDGE('',*,*,#265,.F.);
|
||||||
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#338=ORIENTED_EDGE('',*,*,#266,.F.);
|
||||||
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#339=ORIENTED_EDGE('',*,*,#265,.T.);
|
||||||
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#340=ORIENTED_EDGE('',*,*,#267,.F.);
|
||||||
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|
||||||
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#342=ORIENTED_EDGE('',*,*,#269,.F.);
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||||||
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#343=ORIENTED_EDGE('',*,*,#268,.T.);
|
||||||
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|
||||||
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||||||
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||||||
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|
||||||
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||||||
|
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||||||
|
#350=ORIENTED_EDGE('',*,*,#273,.T.);
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||||||
|
#351=ORIENTED_EDGE('',*,*,#270,.T.);
|
||||||
|
#352=ORIENTED_EDGE('',*,*,#267,.T.);
|
||||||
|
#353=ORIENTED_EDGE('',*,*,#264,.T.);
|
||||||
|
#354=ORIENTED_EDGE('',*,*,#274,.T.);
|
||||||
|
#355=ORIENTED_EDGE('',*,*,#275,.F.);
|
||||||
|
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||||||
|
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||||||
|
#358=ORIENTED_EDGE('',*,*,#278,.T.);
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||||||
|
#359=ORIENTED_EDGE('',*,*,#277,.T.);
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||||||
|
#360=ORIENTED_EDGE('',*,*,#279,.F.);
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||||||
|
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||||||
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#363=ORIENTED_EDGE('',*,*,#280,.T.);
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||||||
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||||||
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||||||
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#366=ORIENTED_EDGE('',*,*,#282,.T.);
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||||||
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#367=ORIENTED_EDGE('',*,*,#279,.T.);
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||||||
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#368=ORIENTED_EDGE('',*,*,#276,.T.);
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||||||
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||||||
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#370=ORIENTED_EDGE('',*,*,#283,.T.);
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||||||
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#371=ORIENTED_EDGE('',*,*,#284,.T.);
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
|
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||||||
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#387=ORIENTED_EDGE('',*,*,#296,.T.);
|
||||||
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||||||
|
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||||||
|
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||||||
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#391=ORIENTED_EDGE('',*,*,#299,.T.);
|
||||||
|
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|
||||||
|
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|
||||||
|
#394=ORIENTED_EDGE('',*,*,#301,.T.);
|
||||||
|
#395=ORIENTED_EDGE('',*,*,#298,.T.);
|
||||||
|
#396=ORIENTED_EDGE('',*,*,#295,.T.);
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
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|
||||||
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
#427=ORIENTED_EDGE('',*,*,#319,.T.);
|
||||||
|
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|
||||||
|
#429=ORIENTED_EDGE('',*,*,#315,.T.);
|
||||||
|
#430=ORIENTED_EDGE('',*,*,#324,.T.);
|
||||||
|
#431=ORIENTED_EDGE('',*,*,#288,.T.);
|
||||||
|
#432=ORIENTED_EDGE('',*,*,#325,.F.);
|
||||||
|
#433=ORIENTED_EDGE('',*,*,#326,.F.);
|
||||||
|
#434=ORIENTED_EDGE('',*,*,#307,.T.);
|
||||||
|
#435=ORIENTED_EDGE('',*,*,#327,.T.);
|
||||||
|
#436=ORIENTED_EDGE('',*,*,#316,.T.);
|
||||||
|
#437=ORIENTED_EDGE('',*,*,#323,.T.);
|
||||||
|
#438=ORIENTED_EDGE('',*,*,#318,.T.);
|
||||||
|
#439=ORIENTED_EDGE('',*,*,#328,.T.);
|
||||||
|
#440=ORIENTED_EDGE('',*,*,#326,.T.);
|
||||||
|
#441=ORIENTED_EDGE('',*,*,#329,.F.);
|
||||||
|
#442=ORIENTED_EDGE('',*,*,#330,.F.);
|
||||||
|
#443=ORIENTED_EDGE('',*,*,#331,.T.);
|
||||||
|
#444=ORIENTED_EDGE('',*,*,#305,.T.);
|
||||||
|
#445=ORIENTED_EDGE('',*,*,#312,.T.);
|
||||||
|
#446=ORIENTED_EDGE('',*,*,#332,.T.);
|
||||||
|
#447=ORIENTED_EDGE('',*,*,#330,.T.);
|
||||||
|
#448=ORIENTED_EDGE('',*,*,#333,.F.);
|
||||||
|
#449=ORIENTED_EDGE('',*,*,#286,.F.);
|
||||||
|
#450=ORIENTED_EDGE('',*,*,#262,.T.);
|
||||||
|
#451=ORIENTED_EDGE('',*,*,#266,.T.);
|
||||||
|
#452=ORIENTED_EDGE('',*,*,#269,.T.);
|
||||||
|
#453=ORIENTED_EDGE('',*,*,#272,.T.);
|
||||||
|
#454=ORIENTED_EDGE('',*,*,#287,.T.);
|
||||||
|
#455=ORIENTED_EDGE('',*,*,#333,.T.);
|
||||||
|
#456=ORIENTED_EDGE('',*,*,#329,.T.);
|
||||||
|
#457=ORIENTED_EDGE('',*,*,#325,.T.);
|
||||||
|
#458=ORIENTED_EDGE('',*,*,#289,.F.);
|
||||||
|
#459=ORIENTED_EDGE('',*,*,#324,.F.);
|
||||||
|
#460=ORIENTED_EDGE('',*,*,#328,.F.);
|
||||||
|
#461=ORIENTED_EDGE('',*,*,#317,.T.);
|
||||||
|
#462=ORIENTED_EDGE('',*,*,#321,.T.);
|
||||||
|
#463=ORIENTED_EDGE('',*,*,#313,.T.);
|
||||||
|
#464=ORIENTED_EDGE('',*,*,#327,.F.);
|
||||||
|
#465=ORIENTED_EDGE('',*,*,#306,.T.);
|
||||||
|
#466=ORIENTED_EDGE('',*,*,#310,.T.);
|
||||||
|
#467=ORIENTED_EDGE('',*,*,#302,.T.);
|
||||||
|
#468=ORIENTED_EDGE('',*,*,#331,.F.);
|
||||||
|
#469=ORIENTED_EDGE('',*,*,#332,.F.);
|
||||||
|
#470=ORIENTED_EDGE('',*,*,#285,.F.);
|
||||||
|
#471=ORIENTED_EDGE('',*,*,#274,.F.);
|
||||||
|
#472=ORIENTED_EDGE('',*,*,#278,.F.);
|
||||||
|
#473=ORIENTED_EDGE('',*,*,#281,.F.);
|
||||||
|
#474=ORIENTED_EDGE('',*,*,#293,.F.);
|
||||||
|
#475=ORIENTED_EDGE('',*,*,#294,.F.);
|
||||||
|
#476=ORIENTED_EDGE('',*,*,#297,.F.);
|
||||||
|
#477=ORIENTED_EDGE('',*,*,#300,.F.);
|
||||||
|
#478=PLANE('',#552);
|
||||||
|
#479=PLANE('',#553);
|
||||||
|
#480=PLANE('',#554);
|
||||||
|
#481=PLANE('',#555);
|
||||||
|
#482=PLANE('',#556);
|
||||||
|
#483=PLANE('',#557);
|
||||||
|
#484=PLANE('',#558);
|
||||||
|
#485=PLANE('',#559);
|
||||||
|
#486=PLANE('',#560);
|
||||||
|
#487=PLANE('',#561);
|
||||||
|
#488=PLANE('',#562);
|
||||||
|
#489=PLANE('',#563);
|
||||||
|
#490=PLANE('',#564);
|
||||||
|
#491=PLANE('',#565);
|
||||||
|
#492=PLANE('',#566);
|
||||||
|
#493=PLANE('',#567);
|
||||||
|
#494=PLANE('',#568);
|
||||||
|
#495=PLANE('',#569);
|
||||||
|
#496=PLANE('',#570);
|
||||||
|
#497=PLANE('',#571);
|
||||||
|
#498=PLANE('',#572);
|
||||||
|
#499=PLANE('',#573);
|
||||||
|
#500=PLANE('',#574);
|
||||||
|
#501=PLANE('',#575);
|
||||||
|
#502=PLANE('',#576);
|
||||||
|
#503=PLANE('',#577);
|
||||||
|
#504=PLANE('',#578);
|
||||||
|
#505=STYLED_ITEM('',(#875),#511);
|
||||||
|
#506=STYLED_ITEM('',(#875),#512);
|
||||||
|
#507=STYLED_ITEM('',(#875),#513);
|
||||||
|
#508=STYLED_ITEM('',(#875),#514);
|
||||||
|
#509=STYLED_ITEM('',(#875),#515);
|
||||||
|
#510=STYLED_ITEM('',(#874),#13);
|
||||||
|
#511=ADVANCED_FACE('',(#15),#478,.T.);
|
||||||
|
#512=ADVANCED_FACE('',(#16),#479,.T.);
|
||||||
|
#513=ADVANCED_FACE('',(#17),#480,.T.);
|
||||||
|
#514=ADVANCED_FACE('',(#18),#481,.T.);
|
||||||
|
#515=ADVANCED_FACE('',(#19),#482,.T.);
|
||||||
|
#516=ADVANCED_FACE('',(#20),#483,.T.);
|
||||||
|
#517=ADVANCED_FACE('',(#21),#484,.T.);
|
||||||
|
#518=ADVANCED_FACE('',(#22),#485,.T.);
|
||||||
|
#519=ADVANCED_FACE('',(#23),#486,.T.);
|
||||||
|
#520=ADVANCED_FACE('',(#24),#487,.T.);
|
||||||
|
#521=ADVANCED_FACE('',(#25),#488,.T.);
|
||||||
|
#522=ADVANCED_FACE('',(#26),#489,.T.);
|
||||||
|
#523=ADVANCED_FACE('',(#27),#490,.T.);
|
||||||
|
#524=ADVANCED_FACE('',(#28),#491,.T.);
|
||||||
|
#525=ADVANCED_FACE('',(#29),#492,.T.);
|
||||||
|
#526=ADVANCED_FACE('',(#30),#493,.T.);
|
||||||
|
#527=ADVANCED_FACE('',(#31),#494,.T.);
|
||||||
|
#528=ADVANCED_FACE('',(#32),#495,.T.);
|
||||||
|
#529=ADVANCED_FACE('',(#33),#496,.T.);
|
||||||
|
#530=ADVANCED_FACE('',(#34),#497,.T.);
|
||||||
|
#531=ADVANCED_FACE('',(#35),#498,.T.);
|
||||||
|
#532=ADVANCED_FACE('',(#36),#499,.T.);
|
||||||
|
#533=ADVANCED_FACE('',(#37),#500,.T.);
|
||||||
|
#534=ADVANCED_FACE('',(#38),#501,.T.);
|
||||||
|
#535=ADVANCED_FACE('',(#39,#14),#502,.T.);
|
||||||
|
#536=ADVANCED_FACE('',(#40),#503,.T.);
|
||||||
|
#537=ADVANCED_FACE('',(#41),#504,.F.);
|
||||||
|
#538=CLOSED_SHELL('',(#511,#512,#513,#514,#515,#516,#517,#518,#519,#520,
|
||||||
|
#521,#522,#523,#524,#525,#526,#527,#528,#529,#530,#531,#532,#533,#534,#535,
|
||||||
|
#536,#537));
|
||||||
|
#539=DERIVED_UNIT_ELEMENT(#541,1.);
|
||||||
|
#540=DERIVED_UNIT_ELEMENT(#860,3.);
|
||||||
|
#541=(
|
||||||
|
MASS_UNIT()
|
||||||
|
NAMED_UNIT(*)
|
||||||
|
SI_UNIT(.KILO.,.GRAM.)
|
||||||
|
);
|
||||||
|
#542=DERIVED_UNIT((#539,#540));
|
||||||
|
#543=MEASURE_REPRESENTATION_ITEM('density measure',
|
||||||
|
POSITIVE_RATIO_MEASURE(7850.),#542);
|
||||||
|
#544=PROPERTY_DEFINITION_REPRESENTATION(#549,#546);
|
||||||
|
#545=PROPERTY_DEFINITION_REPRESENTATION(#550,#547);
|
||||||
|
#546=REPRESENTATION('material name',(#548),#857);
|
||||||
|
#547=REPRESENTATION('density',(#543),#857);
|
||||||
|
#548=DESCRIPTIVE_REPRESENTATION_ITEM('Steel','Steel');
|
||||||
|
#549=PROPERTY_DEFINITION('material property','material name',#867);
|
||||||
|
#550=PROPERTY_DEFINITION('material property','density of part',#867);
|
||||||
|
#551=AXIS2_PLACEMENT_3D('placement',#707,#579,#580);
|
||||||
|
#552=AXIS2_PLACEMENT_3D('',#708,#581,#582);
|
||||||
|
#553=AXIS2_PLACEMENT_3D('',#717,#587,#588);
|
||||||
|
#554=AXIS2_PLACEMENT_3D('',#723,#592,#593);
|
||||||
|
#555=AXIS2_PLACEMENT_3D('',#729,#597,#598);
|
||||||
|
#556=AXIS2_PLACEMENT_3D('',#732,#601,#602);
|
||||||
|
#557=AXIS2_PLACEMENT_3D('',#733,#603,#604);
|
||||||
|
#558=AXIS2_PLACEMENT_3D('',#742,#609,#610);
|
||||||
|
#559=AXIS2_PLACEMENT_3D('',#748,#614,#615);
|
||||||
|
#560=AXIS2_PLACEMENT_3D('',#754,#619,#620);
|
||||||
|
#561=AXIS2_PLACEMENT_3D('',#756,#622,#623);
|
||||||
|
#562=AXIS2_PLACEMENT_3D('',#774,#633,#634);
|
||||||
|
#563=AXIS2_PLACEMENT_3D('',#780,#638,#639);
|
||||||
|
#564=AXIS2_PLACEMENT_3D('',#786,#643,#644);
|
||||||
|
#565=AXIS2_PLACEMENT_3D('',#789,#647,#648);
|
||||||
|
#566=AXIS2_PLACEMENT_3D('',#790,#649,#650);
|
||||||
|
#567=AXIS2_PLACEMENT_3D('',#799,#655,#656);
|
||||||
|
#568=AXIS2_PLACEMENT_3D('',#808,#661,#662);
|
||||||
|
#569=AXIS2_PLACEMENT_3D('',#811,#665,#666);
|
||||||
|
#570=AXIS2_PLACEMENT_3D('',#813,#668,#669);
|
||||||
|
#571=AXIS2_PLACEMENT_3D('',#822,#674,#675);
|
||||||
|
#572=AXIS2_PLACEMENT_3D('',#831,#680,#681);
|
||||||
|
#573=AXIS2_PLACEMENT_3D('',#834,#684,#685);
|
||||||
|
#574=AXIS2_PLACEMENT_3D('',#836,#687,#688);
|
||||||
|
#575=AXIS2_PLACEMENT_3D('',#842,#692,#693);
|
||||||
|
#576=AXIS2_PLACEMENT_3D('',#850,#699,#700);
|
||||||
|
#577=AXIS2_PLACEMENT_3D('',#853,#703,#704);
|
||||||
|
#578=AXIS2_PLACEMENT_3D('',#854,#705,#706);
|
||||||
|
#579=DIRECTION('axis',(0.,0.,1.));
|
||||||
|
#580=DIRECTION('refdir',(1.,0.,0.));
|
||||||
|
#581=DIRECTION('center_axis',(-1.,0.,0.));
|
||||||
|
#582=DIRECTION('ref_axis',(0.,-1.,0.));
|
||||||
|
#583=DIRECTION('',(0.,1.,0.));
|
||||||
|
#584=DIRECTION('',(0.,0.,1.));
|
||||||
|
#585=DIRECTION('',(0.,-1.,0.));
|
||||||
|
#586=DIRECTION('',(0.,0.,1.));
|
||||||
|
#587=DIRECTION('center_axis',(0.,1.,0.));
|
||||||
|
#588=DIRECTION('ref_axis',(-1.,0.,0.));
|
||||||
|
#589=DIRECTION('',(1.,0.,0.));
|
||||||
|
#590=DIRECTION('',(-1.,0.,0.));
|
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||||||
|
#829=CARTESIAN_POINT('',(3.5,0.2,-2.5000000372529));
|
||||||
|
#830=CARTESIAN_POINT('',(4.1,0.,-2.5000000372529));
|
||||||
|
#831=CARTESIAN_POINT('Origin',(4.1,0.,-1.8800000372529));
|
||||||
|
#832=CARTESIAN_POINT('',(4.1,0.,-2.5000000372529));
|
||||||
|
#833=CARTESIAN_POINT('',(4.1,0.2,-2.5000000372529));
|
||||||
|
#834=CARTESIAN_POINT('Origin',(3.8,0.2,-2.1900000372529));
|
||||||
|
#835=CARTESIAN_POINT('',(3.5,0.2,-1.09500001862645));
|
||||||
|
#836=CARTESIAN_POINT('Origin',(3.5,0.,-2.9));
|
||||||
|
#837=CARTESIAN_POINT('',(3.5,0.,-2.9));
|
||||||
|
#838=CARTESIAN_POINT('',(3.5,0.,-2.9));
|
||||||
|
#839=CARTESIAN_POINT('',(3.5,1.35,-2.9));
|
||||||
|
#840=CARTESIAN_POINT('',(3.5,1.35,-2.9));
|
||||||
|
#841=CARTESIAN_POINT('',(3.5,0.,-2.9));
|
||||||
|
#842=CARTESIAN_POINT('Origin',(3.5,0.,0.));
|
||||||
|
#843=CARTESIAN_POINT('',(3.5,0.,0.));
|
||||||
|
#844=CARTESIAN_POINT('',(3.5,0.,0.));
|
||||||
|
#845=CARTESIAN_POINT('',(3.5,1.35,0.));
|
||||||
|
#846=CARTESIAN_POINT('',(3.5,1.35,0.));
|
||||||
|
#847=CARTESIAN_POINT('',(3.5,0.,0.));
|
||||||
|
#848=CARTESIAN_POINT('',(3.5,0.,0.));
|
||||||
|
#849=CARTESIAN_POINT('',(3.5,0.,0.));
|
||||||
|
#850=CARTESIAN_POINT('Origin',(0.,0.,0.));
|
||||||
|
#851=CARTESIAN_POINT('',(0.,0.,0.));
|
||||||
|
#852=CARTESIAN_POINT('',(0.,1.35,0.));
|
||||||
|
#853=CARTESIAN_POINT('Origin',(1.75,1.35,-1.45));
|
||||||
|
#854=CARTESIAN_POINT('Origin',(1.75,0.,-1.45));
|
||||||
|
#855=UNCERTAINTY_MEASURE_WITH_UNIT(LENGTH_MEASURE(0.01),#859,
|
||||||
|
'DISTANCE_ACCURACY_VALUE',
|
||||||
|
'Maximum model space distance between geometric entities at asserted c
|
||||||
|
onnectivities');
|
||||||
|
#856=UNCERTAINTY_MEASURE_WITH_UNIT(LENGTH_MEASURE(0.01),#859,
|
||||||
|
'DISTANCE_ACCURACY_VALUE',
|
||||||
|
'Maximum model space distance between geometric entities at asserted c
|
||||||
|
onnectivities');
|
||||||
|
#857=(
|
||||||
|
GEOMETRIC_REPRESENTATION_CONTEXT(3)
|
||||||
|
GLOBAL_UNCERTAINTY_ASSIGNED_CONTEXT((#855))
|
||||||
|
GLOBAL_UNIT_ASSIGNED_CONTEXT((#859,#861,#862))
|
||||||
|
REPRESENTATION_CONTEXT('','3D')
|
||||||
|
);
|
||||||
|
#858=(
|
||||||
|
GEOMETRIC_REPRESENTATION_CONTEXT(3)
|
||||||
|
GLOBAL_UNCERTAINTY_ASSIGNED_CONTEXT((#856))
|
||||||
|
GLOBAL_UNIT_ASSIGNED_CONTEXT((#859,#861,#862))
|
||||||
|
REPRESENTATION_CONTEXT('','3D')
|
||||||
|
);
|
||||||
|
#859=(
|
||||||
|
LENGTH_UNIT()
|
||||||
|
NAMED_UNIT(*)
|
||||||
|
SI_UNIT(.MILLI.,.METRE.)
|
||||||
|
);
|
||||||
|
#860=(
|
||||||
|
LENGTH_UNIT()
|
||||||
|
NAMED_UNIT(*)
|
||||||
|
SI_UNIT($,.METRE.)
|
||||||
|
);
|
||||||
|
#861=(
|
||||||
|
NAMED_UNIT(*)
|
||||||
|
PLANE_ANGLE_UNIT()
|
||||||
|
SI_UNIT($,.RADIAN.)
|
||||||
|
);
|
||||||
|
#862=(
|
||||||
|
NAMED_UNIT(*)
|
||||||
|
SI_UNIT($,.STERADIAN.)
|
||||||
|
SOLID_ANGLE_UNIT()
|
||||||
|
);
|
||||||
|
#863=SHAPE_DEFINITION_REPRESENTATION(#864,#865);
|
||||||
|
#864=PRODUCT_DEFINITION_SHAPE('',$,#867);
|
||||||
|
#865=SHAPE_REPRESENTATION('',(#551),#857);
|
||||||
|
#866=PRODUCT_DEFINITION_CONTEXT('part definition',#871,'design');
|
||||||
|
#867=PRODUCT_DEFINITION('EVQP7C/L','EVQP7C/L v2',#868,#866);
|
||||||
|
#868=PRODUCT_DEFINITION_FORMATION('',$,#873);
|
||||||
|
#869=PRODUCT_RELATED_PRODUCT_CATEGORY('EVQP7C/L v2','EVQP7C/L v2',(#873));
|
||||||
|
#870=APPLICATION_PROTOCOL_DEFINITION('international standard',
|
||||||
|
'automotive_design',2009,#871);
|
||||||
|
#871=APPLICATION_CONTEXT(
|
||||||
|
'Core Data for Automotive Mechanical Design Process');
|
||||||
|
#872=PRODUCT_CONTEXT('part definition',#871,'mechanical');
|
||||||
|
#873=PRODUCT('EVQP7C/L','EVQP7C/L v2',$,(#872));
|
||||||
|
#874=PRESENTATION_STYLE_ASSIGNMENT((#876));
|
||||||
|
#875=PRESENTATION_STYLE_ASSIGNMENT((#877));
|
||||||
|
#876=SURFACE_STYLE_USAGE(.BOTH.,#878);
|
||||||
|
#877=SURFACE_STYLE_USAGE(.BOTH.,#879);
|
||||||
|
#878=SURFACE_SIDE_STYLE('',(#880));
|
||||||
|
#879=SURFACE_SIDE_STYLE('',(#881));
|
||||||
|
#880=SURFACE_STYLE_FILL_AREA(#882);
|
||||||
|
#881=SURFACE_STYLE_FILL_AREA(#883);
|
||||||
|
#882=FILL_AREA_STYLE('Steel - Satin',(#884));
|
||||||
|
#883=FILL_AREA_STYLE('Plastic - Matte (Black)',(#885));
|
||||||
|
#884=FILL_AREA_STYLE_COLOUR('Steel - Satin',#886);
|
||||||
|
#885=FILL_AREA_STYLE_COLOUR('Plastic - Matte (Black)',#887);
|
||||||
|
#886=COLOUR_RGB('Steel - Satin',0.627450980392157,0.627450980392157,0.627450980392157);
|
||||||
|
#887=COLOUR_RGB('Plastic - Matte (Black)',0.0980392156862745,0.0980392156862745,
|
||||||
|
0.0980392156862745);
|
||||||
|
ENDSEC;
|
||||||
|
END-ISO-10303-21;
|
||||||
9361
pcb/common/footprints.pretty/EVQPU-LC-02K.STEP
Executable file
9361
pcb/common/footprints.pretty/EVQPU-LC-02K.STEP
Executable file
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -1,7 +1,7 @@
|
||||||
{
|
{
|
||||||
"board": {
|
"board": {
|
||||||
"active_layer": 39,
|
"active_layer": 0,
|
||||||
"active_layer_preset": "Back Assembly View",
|
"active_layer_preset": "",
|
||||||
"auto_track_width": false,
|
"auto_track_width": false,
|
||||||
"hidden_netclasses": [],
|
"hidden_netclasses": [],
|
||||||
"hidden_nets": [],
|
"hidden_nets": [],
|
||||||
|
|
@ -19,14 +19,14 @@
|
||||||
"dimensions": false,
|
"dimensions": false,
|
||||||
"footprints": true,
|
"footprints": true,
|
||||||
"graphics": true,
|
"graphics": true,
|
||||||
"keepouts": false,
|
"keepouts": true,
|
||||||
"lockedItems": true,
|
"lockedItems": true,
|
||||||
"otherItems": false,
|
"otherItems": false,
|
||||||
"pads": true,
|
"pads": false,
|
||||||
"text": true,
|
"text": true,
|
||||||
"tracks": true,
|
"tracks": true,
|
||||||
"vias": true,
|
"vias": true,
|
||||||
"zones": false
|
"zones": true
|
||||||
},
|
},
|
||||||
"visible_items": [
|
"visible_items": [
|
||||||
0,
|
0,
|
||||||
|
|
@ -64,7 +64,7 @@
|
||||||
35,
|
35,
|
||||||
36
|
36
|
||||||
],
|
],
|
||||||
"visible_layers": "0015050_00000000",
|
"visible_layers": "00090e0_80000007",
|
||||||
"zone_display_mode": 0
|
"zone_display_mode": 0
|
||||||
},
|
},
|
||||||
"meta": {
|
"meta": {
|
||||||
|
|
|
||||||
|
|
@ -46,7 +46,7 @@
|
||||||
"silk_text_upright": false,
|
"silk_text_upright": false,
|
||||||
"zones": {
|
"zones": {
|
||||||
"45_degree_only": false,
|
"45_degree_only": false,
|
||||||
"min_clearance": 0.11
|
"min_clearance": 0.15
|
||||||
}
|
}
|
||||||
},
|
},
|
||||||
"diff_pair_dimensions": [
|
"diff_pair_dimensions": [
|
||||||
|
|
@ -116,7 +116,7 @@
|
||||||
"max_error": 0.005,
|
"max_error": 0.005,
|
||||||
"min_clearance": 0.0,
|
"min_clearance": 0.0,
|
||||||
"min_connection": 0.0,
|
"min_connection": 0.0,
|
||||||
"min_copper_edge_clearance": 0.024999999999999998,
|
"min_copper_edge_clearance": 0.3,
|
||||||
"min_hole_clearance": 0.0,
|
"min_hole_clearance": 0.0,
|
||||||
"min_hole_to_hole": 0.25,
|
"min_hole_to_hole": 0.25,
|
||||||
"min_microvia_diameter": 0.19999999999999998,
|
"min_microvia_diameter": 0.19999999999999998,
|
||||||
|
|
@ -125,7 +125,7 @@
|
||||||
"min_silk_clearance": 0.0,
|
"min_silk_clearance": 0.0,
|
||||||
"min_text_height": 0.7,
|
"min_text_height": 0.7,
|
||||||
"min_text_thickness": 0.08,
|
"min_text_thickness": 0.08,
|
||||||
"min_through_hole_diameter": 0.19999999999999998,
|
"min_through_hole_diameter": 0.3,
|
||||||
"min_track_width": 0.09999999999999999,
|
"min_track_width": 0.09999999999999999,
|
||||||
"min_via_annular_width": 0.049999999999999996,
|
"min_via_annular_width": 0.049999999999999996,
|
||||||
"min_via_diameter": 0.44999999999999996,
|
"min_via_diameter": 0.44999999999999996,
|
||||||
|
|
@ -179,13 +179,16 @@
|
||||||
0.1,
|
0.1,
|
||||||
0.11,
|
0.11,
|
||||||
0.12,
|
0.12,
|
||||||
|
0.127,
|
||||||
0.13,
|
0.13,
|
||||||
0.15,
|
0.15,
|
||||||
0.2,
|
0.2,
|
||||||
0.3,
|
0.3,
|
||||||
0.5,
|
0.5,
|
||||||
0.6,
|
0.6,
|
||||||
1.0
|
1.0,
|
||||||
|
1.5,
|
||||||
|
2.0
|
||||||
],
|
],
|
||||||
"via_dimensions": [
|
"via_dimensions": [
|
||||||
{
|
{
|
||||||
|
|
@ -442,7 +445,7 @@
|
||||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||||
"track_width": 0.11,
|
"track_width": 0.11,
|
||||||
"via_diameter": 0.45,
|
"via_diameter": 0.45,
|
||||||
"via_drill": 0.2,
|
"via_drill": 0.3,
|
||||||
"wire_width": 6
|
"wire_width": 6
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
|
|
@ -459,7 +462,7 @@
|
||||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||||
"track_width": 0.15,
|
"track_width": 0.15,
|
||||||
"via_diameter": 0.45,
|
"via_diameter": 0.45,
|
||||||
"via_drill": 0.2,
|
"via_drill": 0.3,
|
||||||
"wire_width": 6
|
"wire_width": 6
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
|
|
@ -476,7 +479,7 @@
|
||||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||||
"track_width": 0.11,
|
"track_width": 0.11,
|
||||||
"via_diameter": 0.45,
|
"via_diameter": 0.45,
|
||||||
"via_drill": 0.2,
|
"via_drill": 0.3,
|
||||||
"wire_width": 6
|
"wire_width": 6
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
|
|
@ -493,58 +496,58 @@
|
||||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||||
"track_width": 0.15,
|
"track_width": 0.15,
|
||||||
"via_diameter": 0.45,
|
"via_diameter": 0.45,
|
||||||
"via_drill": 0.2,
|
"via_drill": 0.3,
|
||||||
"wire_width": 6
|
"wire_width": 6
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"bus_width": 12,
|
"bus_width": 12,
|
||||||
"clearance": 0.1,
|
"clearance": 0.127,
|
||||||
"diff_pair_gap": 0.1,
|
"diff_pair_gap": 0.1,
|
||||||
"diff_pair_via_gap": 0.25,
|
"diff_pair_via_gap": 0.25,
|
||||||
"diff_pair_width": 0.1,
|
"diff_pair_width": 0.11,
|
||||||
"line_style": 0,
|
"line_style": 0,
|
||||||
"microvia_diameter": 0.3,
|
"microvia_diameter": 0.3,
|
||||||
"microvia_drill": 0.1,
|
"microvia_drill": 0.1,
|
||||||
"name": "SDRAM_A",
|
"name": "SDRAM_A",
|
||||||
"pcb_color": "rgb(103, 255, 0)",
|
"pcb_color": "rgb(103, 255, 0)",
|
||||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||||
"track_width": 0.1,
|
"track_width": 0.127,
|
||||||
"via_diameter": 0.45,
|
"via_diameter": 0.45,
|
||||||
"via_drill": 0.2,
|
"via_drill": 0.3,
|
||||||
"wire_width": 6
|
"wire_width": 6
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"bus_width": 12,
|
"bus_width": 12,
|
||||||
"clearance": 0.1,
|
"clearance": 0.127,
|
||||||
"diff_pair_gap": 0.1,
|
"diff_pair_gap": 0.1,
|
||||||
"diff_pair_via_gap": 0.25,
|
"diff_pair_via_gap": 0.25,
|
||||||
"diff_pair_width": 0.1,
|
"diff_pair_width": 0.11,
|
||||||
"line_style": 0,
|
"line_style": 0,
|
||||||
"microvia_diameter": 0.3,
|
"microvia_diameter": 0.3,
|
||||||
"microvia_drill": 0.1,
|
"microvia_drill": 0.1,
|
||||||
"name": "SDRAM_H",
|
"name": "SDRAM_H",
|
||||||
"pcb_color": "rgb(255, 252, 0)",
|
"pcb_color": "rgb(255, 252, 0)",
|
||||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||||
"track_width": 0.1,
|
"track_width": 0.127,
|
||||||
"via_diameter": 0.45,
|
"via_diameter": 0.45,
|
||||||
"via_drill": 0.2,
|
"via_drill": 0.3,
|
||||||
"wire_width": 6
|
"wire_width": 6
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"bus_width": 12,
|
"bus_width": 12,
|
||||||
"clearance": 0.1,
|
"clearance": 0.127,
|
||||||
"diff_pair_gap": 0.1,
|
"diff_pair_gap": 0.1,
|
||||||
"diff_pair_via_gap": 0.25,
|
"diff_pair_via_gap": 0.25,
|
||||||
"diff_pair_width": 0.1,
|
"diff_pair_width": 0.11,
|
||||||
"line_style": 0,
|
"line_style": 0,
|
||||||
"microvia_diameter": 0.3,
|
"microvia_diameter": 0.3,
|
||||||
"microvia_drill": 0.1,
|
"microvia_drill": 0.1,
|
||||||
"name": "SDRAM_L",
|
"name": "SDRAM_L",
|
||||||
"pcb_color": "rgb(255, 131, 3)",
|
"pcb_color": "rgb(255, 131, 3)",
|
||||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||||
"track_width": 0.1,
|
"track_width": 0.127,
|
||||||
"via_diameter": 0.45,
|
"via_diameter": 0.45,
|
||||||
"via_drill": 0.2,
|
"via_drill": 0.3,
|
||||||
"wire_width": 6
|
"wire_width": 6
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
|
|
@ -561,7 +564,7 @@
|
||||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||||
"track_width": 0.15,
|
"track_width": 0.15,
|
||||||
"via_diameter": 0.45,
|
"via_diameter": 0.45,
|
||||||
"via_drill": 0.2,
|
"via_drill": 0.3,
|
||||||
"wire_width": 6
|
"wire_width": 6
|
||||||
}
|
}
|
||||||
],
|
],
|
||||||
|
|
@ -569,7 +572,7 @@
|
||||||
"version": 3
|
"version": 3
|
||||||
},
|
},
|
||||||
"net_colors": {
|
"net_colors": {
|
||||||
"+1V1": "rgb(255, 92, 56)",
|
"+1V0": "rgb(255, 92, 56)",
|
||||||
"+1V35": "rgb(185, 61, 143)",
|
"+1V35": "rgb(185, 61, 143)",
|
||||||
"+3V3": "rgb(179, 228, 50)",
|
"+3V3": "rgb(179, 228, 50)",
|
||||||
"+5V": "rgb(255, 122, 107)",
|
"+5V": "rgb(255, 122, 107)",
|
||||||
|
|
@ -578,512 +581,44 @@
|
||||||
"netclass_assignments": null,
|
"netclass_assignments": null,
|
||||||
"netclass_patterns": [
|
"netclass_patterns": [
|
||||||
{
|
{
|
||||||
"netclass": "DP",
|
"netclass": "EPD",
|
||||||
"pattern": "/dp_in/DP0N"
|
"pattern": "/eink/ED*"
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "DP",
|
|
||||||
"pattern": "/dp_in/DP0P"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "DP",
|
|
||||||
"pattern": "/dp_in/DP1N"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "DP",
|
|
||||||
"pattern": "/dp_in/DP1P"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "DP",
|
|
||||||
"pattern": "/dp_in/DPAUXN"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "DP",
|
|
||||||
"pattern": "/dp_in/DPAUXP"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "DP",
|
|
||||||
"pattern": "/dp_in/RX1N"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "DP",
|
|
||||||
"pattern": "/dp_in/RX1NC"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "DP",
|
|
||||||
"pattern": "/dp_in/RX1P"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "DP",
|
|
||||||
"pattern": "/dp_in/RX1PC"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "DP",
|
|
||||||
"pattern": "/dp_in/RX2N"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "DP",
|
|
||||||
"pattern": "/dp_in/RX2NC"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "DP",
|
|
||||||
"pattern": "/dp_in/RX2P"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "DP",
|
|
||||||
"pattern": "/dp_in/RX2PC"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "DP",
|
|
||||||
"pattern": "/dp_in/TX1N"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "DP",
|
|
||||||
"pattern": "/dp_in/TX1NC"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "DP",
|
|
||||||
"pattern": "/dp_in/TX1P"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "DP",
|
|
||||||
"pattern": "/dp_in/TX1PC"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "DP",
|
|
||||||
"pattern": "/dp_in/TX2N"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "DP",
|
|
||||||
"pattern": "/dp_in/TX2NC"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "DP",
|
|
||||||
"pattern": "/dp_in/TX2P"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "DP",
|
|
||||||
"pattern": "/dp_in/TX2PC"
|
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"netclass": "EPD",
|
"netclass": "EPD",
|
||||||
"pattern": "/eink/ED0"
|
"pattern": "EPDC_*"
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"netclass": "SDRAM_A",
|
||||||
|
"pattern": "/fpga_ddr/DRAM_[A|B|C|O|R|W].*"
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"netclass": "EPD",
|
"netclass": "EPD",
|
||||||
"pattern": "/eink/ED1"
|
"pattern": "/eink/ES*"
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "EPD",
|
|
||||||
"pattern": "/eink/ED10"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "EPD",
|
|
||||||
"pattern": "/eink/ED11"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "EPD",
|
|
||||||
"pattern": "/eink/ED12"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "EPD",
|
|
||||||
"pattern": "/eink/ED13"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "EPD",
|
|
||||||
"pattern": "/eink/ED14"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "EPD",
|
|
||||||
"pattern": "/eink/ED15"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "EPD",
|
|
||||||
"pattern": "/eink/ED2"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "EPD",
|
|
||||||
"pattern": "/eink/ED3"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "EPD",
|
|
||||||
"pattern": "/eink/ED4"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "EPD",
|
|
||||||
"pattern": "/eink/ED5"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "EPD",
|
|
||||||
"pattern": "/eink/ED6"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "EPD",
|
|
||||||
"pattern": "/eink/ED7"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "EPD",
|
|
||||||
"pattern": "/eink/ED8"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "EPD",
|
|
||||||
"pattern": "/eink/ED9"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "EPD",
|
|
||||||
"pattern": "/eink/ESDCLK"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "EPD",
|
|
||||||
"pattern": "/eink/ESDLE"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "EPD",
|
|
||||||
"pattern": "/eink/ESDOE"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "EPD",
|
|
||||||
"pattern": "EPDC_D0"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "EPD",
|
|
||||||
"pattern": "EPDC_D1"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "EPD",
|
|
||||||
"pattern": "EPDC_D10"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "EPD",
|
|
||||||
"pattern": "EPDC_D11"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "EPD",
|
|
||||||
"pattern": "EPDC_D12"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "EPD",
|
|
||||||
"pattern": "EPDC_D13"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "EPD",
|
|
||||||
"pattern": "EPDC_D14"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "EPD",
|
|
||||||
"pattern": "EPDC_D15"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "EPD",
|
|
||||||
"pattern": "EPDC_D2"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "EPD",
|
|
||||||
"pattern": "EPDC_D3"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "EPD",
|
|
||||||
"pattern": "EPDC_D4"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "EPD",
|
|
||||||
"pattern": "EPDC_D5"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "EPD",
|
|
||||||
"pattern": "EPDC_D6"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "EPD",
|
|
||||||
"pattern": "EPDC_D7"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "EPD",
|
|
||||||
"pattern": "EPDC_D8"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "EPD",
|
|
||||||
"pattern": "EPDC_D9"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "EPD",
|
|
||||||
"pattern": "EPDC_GDCLK"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "EPD",
|
|
||||||
"pattern": "EPDC_GDOE"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "EPD",
|
|
||||||
"pattern": "EPDC_GDSP"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "EPD",
|
|
||||||
"pattern": "EPDC_SDCE0"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "EPD",
|
|
||||||
"pattern": "EPDC_SDCLK"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "EPD",
|
|
||||||
"pattern": "EPDC_SDLE"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "EPD",
|
|
||||||
"pattern": "EPDC_SDOE"
|
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"netclass": "LVDS",
|
"netclass": "LVDS",
|
||||||
"pattern": "LVDS_EVEN_AN"
|
"pattern": "TMDS*"
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "LVDS",
|
|
||||||
"pattern": "LVDS_EVEN_AP"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "LVDS",
|
|
||||||
"pattern": "LVDS_EVEN_BN"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "LVDS",
|
|
||||||
"pattern": "LVDS_EVEN_BP"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "LVDS",
|
|
||||||
"pattern": "LVDS_EVEN_CN"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "LVDS",
|
|
||||||
"pattern": "LVDS_EVEN_CP"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "LVDS",
|
|
||||||
"pattern": "LVDS_ODD_AN"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "LVDS",
|
|
||||||
"pattern": "LVDS_ODD_AP"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "LVDS",
|
|
||||||
"pattern": "LVDS_ODD_BN"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "LVDS",
|
|
||||||
"pattern": "LVDS_ODD_BP"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "LVDS",
|
|
||||||
"pattern": "LVDS_ODD_CKN"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "LVDS",
|
|
||||||
"pattern": "LVDS_ODD_CKP"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "LVDS",
|
|
||||||
"pattern": "LVDS_ODD_CN"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "LVDS",
|
|
||||||
"pattern": "LVDS_ODD_CP"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "SDRAM_A",
|
|
||||||
"pattern": "/fpga_ddr/DRAM_ADDR0"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "SDRAM_A",
|
|
||||||
"pattern": "/fpga_ddr/DRAM_ADDR1"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "SDRAM_A",
|
|
||||||
"pattern": "/fpga_ddr/DRAM_ADDR10"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "SDRAM_A",
|
|
||||||
"pattern": "/fpga_ddr/DRAM_ADDR11"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "SDRAM_A",
|
|
||||||
"pattern": "/fpga_ddr/DRAM_ADDR12"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "SDRAM_A",
|
|
||||||
"pattern": "/fpga_ddr/DRAM_ADDR13"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "SDRAM_A",
|
|
||||||
"pattern": "/fpga_ddr/DRAM_ADDR14"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "SDRAM_A",
|
|
||||||
"pattern": "/fpga_ddr/DRAM_ADDR2"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "SDRAM_A",
|
|
||||||
"pattern": "/fpga_ddr/DRAM_ADDR3"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "SDRAM_A",
|
|
||||||
"pattern": "/fpga_ddr/DRAM_ADDR4"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "SDRAM_A",
|
|
||||||
"pattern": "/fpga_ddr/DRAM_ADDR5"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "SDRAM_A",
|
|
||||||
"pattern": "/fpga_ddr/DRAM_ADDR6"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "SDRAM_A",
|
|
||||||
"pattern": "/fpga_ddr/DRAM_ADDR7"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "SDRAM_A",
|
|
||||||
"pattern": "/fpga_ddr/DRAM_ADDR8"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "SDRAM_A",
|
|
||||||
"pattern": "/fpga_ddr/DRAM_ADDR9"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "SDRAM_A",
|
|
||||||
"pattern": "/fpga_ddr/DRAM_BA0"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "SDRAM_A",
|
|
||||||
"pattern": "/fpga_ddr/DRAM_BA1"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "SDRAM_A",
|
|
||||||
"pattern": "/fpga_ddr/DRAM_BA2"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "SDRAM_A",
|
|
||||||
"pattern": "/fpga_ddr/DRAM_CASB"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "SDRAM_A",
|
|
||||||
"pattern": "/fpga_ddr/DRAM_CKE"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "SDRAM_A",
|
|
||||||
"pattern": "/fpga_ddr/DRAM_CKN"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "SDRAM_A",
|
|
||||||
"pattern": "/fpga_ddr/DRAM_CKP"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "SDRAM_A",
|
|
||||||
"pattern": "/fpga_ddr/DRAM_CSB"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "SDRAM_A",
|
|
||||||
"pattern": "/fpga_ddr/DRAM_ODT"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "SDRAM_A",
|
|
||||||
"pattern": "/fpga_ddr/DRAM_RASB"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "SDRAM_A",
|
|
||||||
"pattern": "/fpga_ddr/DRAM_RST"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "SDRAM_A",
|
|
||||||
"pattern": "/fpga_ddr/DRAM_WEB"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "SDRAM_H",
|
|
||||||
"pattern": "/fpga_ddr/DRAM_DATA10"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "SDRAM_H",
|
|
||||||
"pattern": "/fpga_ddr/DRAM_DATA11"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "SDRAM_H",
|
|
||||||
"pattern": "/fpga_ddr/DRAM_DATA12"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "SDRAM_H",
|
|
||||||
"pattern": "/fpga_ddr/DRAM_DATA13"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "SDRAM_H",
|
|
||||||
"pattern": "/fpga_ddr/DRAM_DATA14"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "SDRAM_H",
|
|
||||||
"pattern": "/fpga_ddr/DRAM_DATA15"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "SDRAM_H",
|
|
||||||
"pattern": "/fpga_ddr/DRAM_DATA8"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "SDRAM_H",
|
|
||||||
"pattern": "/fpga_ddr/DRAM_DATA9"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "SDRAM_H",
|
|
||||||
"pattern": "/fpga_ddr/DRAM_UDM"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "SDRAM_H",
|
|
||||||
"pattern": "/fpga_ddr/DRAM_UDQSN"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "SDRAM_H",
|
|
||||||
"pattern": "/fpga_ddr/DRAM_UDQSP"
|
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"netclass": "SDRAM_L",
|
"netclass": "SDRAM_L",
|
||||||
"pattern": "/fpga_ddr/DRAM_DATA0"
|
"pattern": "/fpga_ddr/DRAM_DATA[0-7]"
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"netclass": "SDRAM_L",
|
"netclass": "SDRAM_L",
|
||||||
"pattern": "/fpga_ddr/DRAM_DATA1"
|
"pattern": "/fpga_ddr/DRAM_L*"
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"netclass": "SDRAM_L",
|
"netclass": "SDRAM_H",
|
||||||
"pattern": "/fpga_ddr/DRAM_DATA2"
|
"pattern": "/fpga_ddr/DRAM_DATA[8-9]"
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"netclass": "SDRAM_L",
|
"netclass": "SDRAM_H",
|
||||||
"pattern": "/fpga_ddr/DRAM_DATA3"
|
"pattern": "/fpga_ddr/DRAM_DATA1[0-5]"
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"netclass": "SDRAM_L",
|
"netclass": "SDRAM_H",
|
||||||
"pattern": "/fpga_ddr/DRAM_DATA4"
|
"pattern": "/fpga_ddr/DRAM_U*"
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "SDRAM_L",
|
|
||||||
"pattern": "/fpga_ddr/DRAM_DATA5"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "SDRAM_L",
|
|
||||||
"pattern": "/fpga_ddr/DRAM_DATA6"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "SDRAM_L",
|
|
||||||
"pattern": "/fpga_ddr/DRAM_DATA7"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "SDRAM_L",
|
|
||||||
"pattern": "/fpga_ddr/DRAM_LDM"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "SDRAM_L",
|
|
||||||
"pattern": "/fpga_ddr/DRAM_LDQSN"
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"netclass": "SDRAM_L",
|
|
||||||
"pattern": "/fpga_ddr/DRAM_LDQSP"
|
|
||||||
}
|
}
|
||||||
]
|
]
|
||||||
},
|
},
|
||||||
|
|
@ -1093,13 +628,13 @@
|
||||||
"idf": "",
|
"idf": "",
|
||||||
"netlist": "",
|
"netlist": "",
|
||||||
"specctra_dsn": "",
|
"specctra_dsn": "",
|
||||||
"step": "",
|
"step": "pcb.step",
|
||||||
"vrml": ""
|
"vrml": ""
|
||||||
},
|
},
|
||||||
"page_layout_descr_file": ""
|
"page_layout_descr_file": ""
|
||||||
},
|
},
|
||||||
"schematic": {
|
"schematic": {
|
||||||
"annotate_start_num": 400,
|
"annotate_start_num": 0,
|
||||||
"drawing": {
|
"drawing": {
|
||||||
"dashed_lines_dash_length_ratio": 12.0,
|
"dashed_lines_dash_length_ratio": 12.0,
|
||||||
"dashed_lines_gap_length_ratio": 3.0,
|
"dashed_lines_gap_length_ratio": 3.0,
|
||||||
|
|
@ -1170,8 +705,12 @@
|
||||||
"dp_in"
|
"dp_in"
|
||||||
],
|
],
|
||||||
[
|
[
|
||||||
"f69cfcc8-f979-4315-84ee-316a84fb66a2",
|
"d0757a0a-c868-475e-8221-24a5e99d32b9",
|
||||||
"mcu"
|
"mcu"
|
||||||
|
],
|
||||||
|
[
|
||||||
|
"1afc3cb7-9ace-435f-9131-835660c51142",
|
||||||
|
"tmds_in"
|
||||||
]
|
]
|
||||||
],
|
],
|
||||||
"text_variables": {}
|
"text_variables": {}
|
||||||
|
|
|
||||||
|
|
@ -5,10 +5,10 @@
|
||||||
(paper "A4")
|
(paper "A4")
|
||||||
|
|
||||||
(title_block
|
(title_block
|
||||||
(title "Caster EPDC")
|
(title "Glider Lite")
|
||||||
(date "2022-07-03")
|
(date "2023-12-24")
|
||||||
(rev "R0.4")
|
(rev "R0.7")
|
||||||
(company "Copyright 2022 Modos / Engineer: Wenting Zhang")
|
(company "Copyright 2023 Modos / Engineer: Wenting Zhang")
|
||||||
)
|
)
|
||||||
|
|
||||||
(lib_symbols
|
(lib_symbols
|
||||||
|
|
@ -23,24 +23,33 @@
|
||||||
(effects (font (size 2.54 2.54)) (justify left bottom))
|
(effects (font (size 2.54 2.54)) (justify left bottom))
|
||||||
(uuid 558a13be-3757-4ba7-9c3e-24eef7c78d0f)
|
(uuid 558a13be-3757-4ba7-9c3e-24eef7c78d0f)
|
||||||
)
|
)
|
||||||
(text "Microcontroller" (at 35.56 90.17 0)
|
(text "USB Type-C Input" (at 35.56 78.74 0)
|
||||||
(effects (font (size 2.54 2.54)) (justify left bottom))
|
(effects (font (size 2.54 2.54)) (justify left bottom))
|
||||||
(uuid c27f5386-efb4-4ccf-b667-fcc6d3db883b)
|
(uuid 5ea0662e-1e83-4654-bdb0-1f5b1245a5b9)
|
||||||
|
)
|
||||||
|
(text "Microcontroller" (at 35.56 101.6 0)
|
||||||
|
(effects (font (size 2.54 2.54)) (justify left bottom))
|
||||||
|
(uuid b67963c3-f29b-47c7-8922-33e72e8d5f68)
|
||||||
)
|
)
|
||||||
(text "Display" (at 35.56 55.88 0)
|
(text "Display" (at 35.56 55.88 0)
|
||||||
(effects (font (size 2.54 2.54)) (justify left bottom))
|
(effects (font (size 2.54 2.54)) (justify left bottom))
|
||||||
(uuid d2b3e5ed-56f7-4162-ab02-9bde306dbf5a)
|
(uuid d2b3e5ed-56f7-4162-ab02-9bde306dbf5a)
|
||||||
)
|
)
|
||||||
|
(text "I2C Addresses\n0100010 FUSB302B\n1100000 PTN3460BS\n1001100 ADV7611"
|
||||||
|
(at 33.02 185.42 0)
|
||||||
|
(effects (font (size 1.27 1.27)) (justify left bottom))
|
||||||
|
(uuid ed4a6249-8bd7-4d22-9dec-f83bb6e206e1)
|
||||||
|
)
|
||||||
(text "FPGA Core" (at 35.56 44.45 0)
|
(text "FPGA Core" (at 35.56 44.45 0)
|
||||||
(effects (font (size 2.54 2.54)) (justify left bottom))
|
(effects (font (size 2.54 2.54)) (justify left bottom))
|
||||||
(uuid edafe42e-7b4b-443d-9c19-73868867df97)
|
(uuid edafe42e-7b4b-443d-9c19-73868867df97)
|
||||||
)
|
)
|
||||||
(text "USB Type-C Input" (at 35.56 78.74 0)
|
(text "TMDS Input" (at 35.56 90.17 0)
|
||||||
(effects (font (size 2.54 2.54)) (justify left bottom))
|
(effects (font (size 2.54 2.54)) (justify left bottom))
|
||||||
(uuid fbc25d2d-afe2-4ffb-9abb-3b9e35c79f93)
|
(uuid fbc25d2d-afe2-4ffb-9abb-3b9e35c79f93)
|
||||||
)
|
)
|
||||||
|
|
||||||
(sheet (at 33.02 27.94) (size 54.61 6.35) (fields_autoplaced)
|
(sheet (at 33.02 27.94) (size 53.34 6.35) (fields_autoplaced)
|
||||||
(stroke (width 0.1524) (type solid))
|
(stroke (width 0.1524) (type solid))
|
||||||
(fill (color 0 0 0 0.0000))
|
(fill (color 0 0 0 0.0000))
|
||||||
(uuid 0606a719-6980-4867-837f-aa642737d361)
|
(uuid 0606a719-6980-4867-837f-aa642737d361)
|
||||||
|
|
@ -57,7 +66,24 @@
|
||||||
)
|
)
|
||||||
)
|
)
|
||||||
|
|
||||||
(sheet (at 33.02 39.37) (size 54.61 6.35) (fields_autoplaced)
|
(sheet (at 33.02 85.09) (size 53.34 6.35) (fields_autoplaced)
|
||||||
|
(stroke (width 0.1524) (type solid))
|
||||||
|
(fill (color 0 0 0 0.0000))
|
||||||
|
(uuid 1afc3cb7-9ace-435f-9131-835660c51142)
|
||||||
|
(property "Sheetname" "tmds_in" (at 33.02 84.3784 0)
|
||||||
|
(effects (font (size 1.27 1.27)) (justify left bottom))
|
||||||
|
)
|
||||||
|
(property "Sheetfile" "tmds_in.kicad_sch" (at 33.02 92.0246 0)
|
||||||
|
(effects (font (size 1.27 1.27)) (justify left top))
|
||||||
|
)
|
||||||
|
(instances
|
||||||
|
(project "pcb"
|
||||||
|
(path "/4654897e-3e2f-4522-96c3-20b19803c088" (page "8"))
|
||||||
|
)
|
||||||
|
)
|
||||||
|
)
|
||||||
|
|
||||||
|
(sheet (at 33.02 39.37) (size 53.34 6.35) (fields_autoplaced)
|
||||||
(stroke (width 0.1524) (type solid))
|
(stroke (width 0.1524) (type solid))
|
||||||
(fill (color 0 0 0 0.0000))
|
(fill (color 0 0 0 0.0000))
|
||||||
(uuid 35d2a4e1-1cb2-4b6c-a7fb-e3a9449d4ff3)
|
(uuid 35d2a4e1-1cb2-4b6c-a7fb-e3a9449d4ff3)
|
||||||
|
|
@ -74,7 +100,7 @@
|
||||||
)
|
)
|
||||||
)
|
)
|
||||||
|
|
||||||
(sheet (at 33.02 73.66) (size 54.61 6.35) (fields_autoplaced)
|
(sheet (at 33.02 73.66) (size 53.34 6.35) (fields_autoplaced)
|
||||||
(stroke (width 0.1524) (type solid))
|
(stroke (width 0.1524) (type solid))
|
||||||
(fill (color 0 0 0 0.0000))
|
(fill (color 0 0 0 0.0000))
|
||||||
(uuid 80373716-d41f-4f06-92dd-577434075703)
|
(uuid 80373716-d41f-4f06-92dd-577434075703)
|
||||||
|
|
@ -86,12 +112,12 @@
|
||||||
)
|
)
|
||||||
(instances
|
(instances
|
||||||
(project "pcb"
|
(project "pcb"
|
||||||
(path "/4654897e-3e2f-4522-96c3-20b19803c088" (page "7"))
|
(path "/4654897e-3e2f-4522-96c3-20b19803c088" (page "5"))
|
||||||
)
|
)
|
||||||
)
|
)
|
||||||
)
|
)
|
||||||
|
|
||||||
(sheet (at 33.02 62.23) (size 54.61 6.35) (fields_autoplaced)
|
(sheet (at 33.02 62.23) (size 53.34 6.35) (fields_autoplaced)
|
||||||
(stroke (width 0.1524) (type solid))
|
(stroke (width 0.1524) (type solid))
|
||||||
(fill (color 0 0 0 0.0000))
|
(fill (color 0 0 0 0.0000))
|
||||||
(uuid 866a5b4a-453a-413a-94a2-5e610f40d8dd)
|
(uuid 866a5b4a-453a-413a-94a2-5e610f40d8dd)
|
||||||
|
|
@ -103,12 +129,12 @@
|
||||||
)
|
)
|
||||||
(instances
|
(instances
|
||||||
(project "pcb"
|
(project "pcb"
|
||||||
(path "/4654897e-3e2f-4522-96c3-20b19803c088" (page "5"))
|
(path "/4654897e-3e2f-4522-96c3-20b19803c088" (page "4"))
|
||||||
)
|
)
|
||||||
)
|
)
|
||||||
)
|
)
|
||||||
|
|
||||||
(sheet (at 33.02 50.8) (size 54.61 6.35) (fields_autoplaced)
|
(sheet (at 33.02 50.8) (size 53.34 6.35) (fields_autoplaced)
|
||||||
(stroke (width 0.1524) (type solid))
|
(stroke (width 0.1524) (type solid))
|
||||||
(fill (color 0 0 0 0.0000))
|
(fill (color 0 0 0 0.0000))
|
||||||
(uuid b1d5941d-0481-47a2-a434-0b8e587a166a)
|
(uuid b1d5941d-0481-47a2-a434-0b8e587a166a)
|
||||||
|
|
@ -125,19 +151,19 @@
|
||||||
)
|
)
|
||||||
)
|
)
|
||||||
|
|
||||||
(sheet (at 33.02 85.09) (size 54.61 6.35) (fields_autoplaced)
|
(sheet (at 33.02 96.52) (size 53.34 6.35) (fields_autoplaced)
|
||||||
(stroke (width 0.1524) (type solid))
|
(stroke (width 0.1524) (type solid))
|
||||||
(fill (color 0 0 0 0.0000))
|
(fill (color 0 0 0 0.0000))
|
||||||
(uuid f69cfcc8-f979-4315-84ee-316a84fb66a2)
|
(uuid d0757a0a-c868-475e-8221-24a5e99d32b9)
|
||||||
(property "Sheetname" "mcu" (at 33.02 84.3784 0)
|
(property "Sheetname" "mcu" (at 33.02 95.8084 0)
|
||||||
(effects (font (size 1.27 1.27)) (justify left bottom))
|
(effects (font (size 1.27 1.27)) (justify left bottom))
|
||||||
)
|
)
|
||||||
(property "Sheetfile" "mcu.kicad_sch" (at 33.02 92.0246 0)
|
(property "Sheetfile" "mcu.kicad_sch" (at 33.02 103.4546 0)
|
||||||
(effects (font (size 1.27 1.27)) (justify left top))
|
(effects (font (size 1.27 1.27)) (justify left top))
|
||||||
)
|
)
|
||||||
(instances
|
(instances
|
||||||
(project "pcb"
|
(project "pcb"
|
||||||
(path "/4654897e-3e2f-4522-96c3-20b19803c088" (page "7"))
|
(path "/4654897e-3e2f-4522-96c3-20b19803c088" (page "6"))
|
||||||
)
|
)
|
||||||
)
|
)
|
||||||
)
|
)
|
||||||
|
|
|
||||||
File diff suppressed because it is too large
Load diff
|
|
@ -1,3 +1,4 @@
|
||||||
(sym_lib_table
|
(sym_lib_table
|
||||||
|
(version 7)
|
||||||
(lib (name "symbols")(type "KiCad")(uri "${KIPRJMOD}/../common/symbols.kicad_sym")(options "")(descr ""))
|
(lib (name "symbols")(type "KiCad")(uri "${KIPRJMOD}/../common/symbols.kicad_sym")(options "")(descr ""))
|
||||||
)
|
)
|
||||||
|
|
|
||||||
4455
pcb/mainboard/tmds_in.kicad_sch
Normal file
4455
pcb/mainboard/tmds_in.kicad_sch
Normal file
File diff suppressed because it is too large
Load diff
Loading…
Reference in a new issue