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pcb: r0p6

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This commit is contained in:
Wenting Zhang 2023-06-25 22:37:00 -04:00
parent eb59d7f209
commit d6f6bd5514
13 changed files with 58676 additions and 43800 deletions
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77
pcb/common/footprints.pretty/USB-306A-B-SU.kicad_mod Normal file
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@ -0,0 +1,77 @@
(footprint "USB-306A-B-SU" (version 20221018) (generator pcbnew)
(layer "F.Cu")
(descr "USB TYPE C, RA RCPT PCB, Hybrid, https://www.amphenolcanada.com/StockAvailabilityPrice.aspx?From=&PartNum=12401548E4%7e2A")
(tags "USB C Type-C Receptacle Hybrid")
(attr smd)
(fp_text reference "REF**" (at 0 -6.36) (layer "F.SilkS")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp cc9e4c39-bea7-4e94-9c24-79713f9cc7d3)
)
(fp_text value "USB-306A-B-SU" (at 0 6.14) (layer "F.Fab")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp 7532bfbd-593b-4c4b-abe0-9db5aba2e09b)
)
(fp_text user "${REFERENCE}" (at 0 0) (layer "F.Fab")
(effects (font (size 1 1) (thickness 0.1)))
(tstamp fbad371e-9c1d-46a8-95d7-2d0a493b34e8)
)
(fp_line (start -4.75 -5.37) (end -4.75 0.5)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp c2931665-9613-433c-aa14-e9abf85d36ae))
(fp_line (start -4.75 -5.37) (end -3.25 -5.37)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp f90c6680-2cd6-4066-a128-2c8ebe03fab8))
(fp_line (start 3.25 -5.37) (end 4.75 -5.37)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp ce47fb52-c99f-4a10-ab39-dda3800eb41a))
(fp_line (start 4.75 -5.37) (end 4.75 0.5)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 7e708e34-9e65-4bc4-84d9-f33cdbc82037))
(fp_line (start -5.39 -5.87) (end 5.39 -5.87)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 7e6f05fe-1ec7-4741-9b94-1aad4bfad894))
(fp_line (start -5.39 4.5) (end -5.39 -5.87)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp f413cec4-7e61-490b-87ea-5ea1f59c9e57))
(fp_line (start 5.39 -5.87) (end 5.39 4.5)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp edd86c06-80c4-475d-8ac0-b7fee2fe3517))
(fp_line (start 5.39 4.5) (end -5.39 4.5)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 8aff6d64-1c61-4c4a-ae06-88f52f8c1ad1))
(fp_line (start -4.6 -5.22) (end 4.6 -5.22)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 997697f8-ecfc-49c3-bab2-2067ad344e14))
(fp_line (start -4.6 3.81) (end -4.6 -5.22)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp c137d5f6-2825-4870-869b-1f19ad03e570))
(fp_line (start -4.6 3.81) (end 4.6 3.81)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 28190817-4423-4e66-a398-129a3525923d))
(fp_line (start 4.6 3.81) (end 4.6 -5.22)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 1bf977d5-ba47-4842-9234-360e3690a628))
(pad "" np_thru_hole circle (at -3.6 -4.36) (size 0.65 0.65) (drill 0.65) (layers "*.Cu" "*.Mask") (tstamp 5c20b50b-02aa-487a-8116-0c18582b1e54))
(pad "" np_thru_hole oval (at 3.6 -4.36) (size 0.95 0.65) (drill oval 0.95 0.65) (layers "*.Cu" "*.Mask") (tstamp db70c4b3-5c7b-49db-973b-e4035024016d))
(pad "A1" smd rect (at -2.75 -5.02) (size 0.3 0.7) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 455f66be-5159-4e48-ba4a-a9918c1770b6))
(pad "A2" smd rect (at -2.25 -5.02) (size 0.3 0.7) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 79311372-68c4-4bab-a639-123bbddf4c73))
(pad "A3" smd rect (at -1.75 -5.02) (size 0.3 0.7) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 1676ebc9-9ffa-45e7-814e-a0f6b2b3194d))
(pad "A4" smd rect (at -1.25 -5.02) (size 0.3 0.7) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp f4ab1667-0bfb-4604-8150-fdbdb4506122))
(pad "A5" smd rect (at -0.75 -5.02) (size 0.3 0.7) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 5f55ce74-3f7c-4921-97a3-e2c82dab17a8))
(pad "A6" smd rect (at -0.25 -5.02) (size 0.3 0.7) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 6bcf2b8a-7935-42d7-a5e4-efe216daffb3))
(pad "A7" smd rect (at 0.25 -5.02) (size 0.3 0.7) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp f8115e39-cc50-4ac3-af5b-daf539ffa90a))
(pad "A8" smd rect (at 0.75 -5.02) (size 0.3 0.7) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 9f98d70d-9b82-4cfd-8e6c-9a5a2dbdf850))
(pad "A9" smd rect (at 1.25 -5.02) (size 0.3 0.7) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 04e19e33-5ac7-4b55-88ab-2932180f8f92))
(pad "A10" smd rect (at 1.75 -5.02) (size 0.3 0.7) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 05c149aa-b044-4f11-8651-9576e24eecdf))
(pad "A11" smd rect (at 2.25 -5.02) (size 0.3 0.7) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 464a2c29-9460-4887-a3ad-a2a20afaa63c))
(pad "A12" smd rect (at 2.75 -5.02) (size 0.3 0.7) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 732487dc-dce3-4f7d-9571-85e0c7778b06))
(pad "B1" thru_hole circle (at 2.8 -3.71) (size 0.65 0.65) (drill 0.4) (layers "*.Cu" "*.Mask") (tstamp 431e87f3-2b07-41bd-a79d-80b530c9f5ee))
(pad "B2" thru_hole circle (at 2.4 -3.01) (size 0.65 0.65) (drill 0.4) (layers "*.Cu" "*.Mask") (tstamp 86fb9f59-f584-4146-b2b5-adc7715fe886))
(pad "B3" thru_hole circle (at 1.6 -3.01) (size 0.65 0.65) (drill 0.4) (layers "*.Cu" "*.Mask") (tstamp 5b8e4f21-352b-42f5-b955-ba357534b41e))
(pad "B4" thru_hole circle (at 1.2 -3.71) (size 0.65 0.65) (drill 0.4) (layers "*.Cu" "*.Mask") (tstamp 17ca9f6b-8544-4981-a45e-2c06bd8024f6))
(pad "B5" thru_hole circle (at 0.8 -3.01) (size 0.65 0.65) (drill 0.4) (layers "*.Cu" "*.Mask") (tstamp b963b755-7b45-4c8e-ad4c-b232259bcd59))
(pad "B6" thru_hole circle (at 0.4 -3.71) (size 0.65 0.65) (drill 0.4) (layers "*.Cu" "*.Mask") (tstamp f503c65f-671a-4782-abc8-0cccab8852f4))
(pad "B7" thru_hole circle (at -0.4 -3.71) (size 0.65 0.65) (drill 0.4) (layers "*.Cu" "*.Mask") (tstamp 915f4772-9b94-4798-a740-3011a0736735))
(pad "B8" thru_hole circle (at -0.8 -3.01) (size 0.65 0.65) (drill 0.4) (layers "*.Cu" "*.Mask") (tstamp 2ef8f15a-d2e1-4e9d-85bf-c67d9b011e81))
(pad "B9" thru_hole circle (at -1.2 -3.71) (size 0.65 0.65) (drill 0.4) (layers "*.Cu" "*.Mask") (tstamp 4e6e1d06-e61d-49c9-b3de-2a2e4699d04c))
(pad "B10" thru_hole circle (at -1.6 -3.01) (size 0.65 0.65) (drill 0.4) (layers "*.Cu" "*.Mask") (tstamp 96b737d4-8058-46f4-9419-eeb545a00b6d))
(pad "B11" thru_hole circle (at -2.4 -3.01) (size 0.65 0.65) (drill 0.4) (layers "*.Cu" "*.Mask") (tstamp 8ea114ee-b284-4437-a1dd-8a72f55a83da))
(pad "B12" thru_hole circle (at -2.8 -3.71) (size 0.65 0.65) (drill 0.4) (layers "*.Cu" "*.Mask") (tstamp 3eef3f4c-3406-4c3f-ad8b-a41ff605994c))
(pad "S1" thru_hole oval (at -4.49 1.28) (size 0.8 1.4) (drill oval 0.5 1.1) (layers "*.Cu" "*.Mask") (tstamp fb388ee2-eae3-4c1e-8b47-87883b962efa))
(pad "S1" thru_hole oval (at -4.13 -3.11) (size 0.8 1.4) (drill oval 0.5 1.1) (layers "*.Cu" "*.Mask") (tstamp fde7d970-0215-4726-a454-86bbded93072))
(pad "S1" thru_hole oval (at 4.13 -3.11) (size 0.8 1.4) (drill oval 0.5 1.1) (layers "*.Cu" "*.Mask") (tstamp db8bd402-e5c5-4dbf-b3c9-879f427d3681))
(pad "S1" thru_hole oval (at 4.49 1.28) (size 0.8 1.4) (drill oval 0.5 1.1) (layers "*.Cu" "*.Mask") (tstamp c7079066-c4a6-4757-9480-44b2ba6074fc))
(model "${KICAD6_3DMODEL_DIR}/Connector_USB.3dshapes/USB_C_Receptacle_Amphenol_12401548E4-2A.wrl"
(offset (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)

22042
pcb/common/symbols.bak Executable file
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1901
pcb/mainboard/dp_in.kicad_sch
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5326
pcb/mainboard/eink.kicad_sch
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9
pcb/mainboard/fp-info-cache
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@ -1,4 +1,4 @@
37621078134234
39436226710237
footprints
472720024
47272-0024
@ -154,6 +154,13 @@ SATA, Receptacle, Cable-to-Board, 22 Position, 7P + 15P, Standard Connector Prof
24
23
footprints
USB-306A-B-SU
USB TYPE C, RA RCPT PCB, Hybrid, https://www.amphenolcanada.com/StockAvailabilityPrice.aspx?From=&PartNum=12401548E4%7e2A
USB C Type-C Receptacle Hybrid
0
28
25
footprints
Xilinx_FTG256
Artix-7 BGA, 16x16 grid, 17x17mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=269, NSMD pad definition Appendix A
BGA 256 1 FT256 FTG256

1391
pcb/mainboard/fpga.kicad_sch
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1974
pcb/mainboard/fpga_ddr.kicad_sch
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1222
pcb/mainboard/mcu.kicad_sch
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64282
pcb/mainboard/pcb.kicad_pcb
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14
pcb/mainboard/pcb.kicad_prl
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@ -1,12 +1,14 @@
{
"board": {
"active_layer": 31,
"active_layer_preset": "",
"active_layer": 39,
"active_layer_preset": "Back Assembly View",
"auto_track_width": false,
"hidden_netclasses": [],
"hidden_nets": [],
"high_contrast_mode": 0,
"net_color_mode": 1,
"opacity": {
"images": 0.6,
"pads": 1.0,
"tracks": 1.0,
"vias": 1.0,
@ -16,14 +18,14 @@
"selection_filter": {
"dimensions": false,
"footprints": true,
"graphics": false,
"graphics": true,
"keepouts": false,
"lockedItems": true,
"otherItems": false,
"pads": false,
"pads": true,
"text": true,
"tracks": true,
"vias": false,
"vias": true,
"zones": false
},
"visible_items": [
@ -62,7 +64,7 @@
35,
36
],
"visible_layers": "ffcffff_ffffffff",
"visible_layers": "00150d0_00000000",
"zone_display_mode": 0
},
"meta": {

767
pcb/mainboard/pcb.kicad_pro
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@ -1,5 +1,6 @@
{
"board": {
"3dviewports": [],
"design_settings": {
"defaults": {
"board_outline_line_width": 0.049999999999999996,
@ -55,30 +56,33 @@
"width": 0.0
}
],
"drc_exclusions": [
"clearance|111375000|70787500|8043308d-7c45-4b18-b445-5e6c4387d7b4|a85ba101-eea1-4cbe-a2a6-47823743aeb3",
"clearance|111425000|71350000|b54c3c8d-e9c4-411e-aa64-48334be98732|a85ba101-eea1-4cbe-a2a6-47823743aeb3"
],
"drc_exclusions": [],
"meta": {
"version": 2
},
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"connection_width": "warning",
"copper_edge_clearance": "error",
"copper_sliver": "warning",
"courtyards_overlap": "warning",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"footprint": "error",
"footprint_type_mismatch": "error",
"hole_clearance": "error",
"hole_near_hole": "error",
"invalid_outline": "error",
"isolated_copper": "warning",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"length_out_of_range": "error",
"lib_footprint_issues": "warning",
"lib_footprint_mismatch": "warning",
"malformed_courtyard": "error",
"microvia_drill_out_of_range": "error",
"missing_courtyard": "ignore",
@ -88,9 +92,14 @@
"padstack": "error",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
"silk_edge_clearance": "warning",
"silk_over_copper": "error",
"silk_overlap": "error",
"skew_out_of_range": "error",
"solder_mask_bridge": "error",
"starved_thermal": "error",
"text_height": "warning",
"text_thickness": "warning",
"through_hole_pad_without_hole": "error",
"too_many_vias": "error",
"track_dangling": "warning",
@ -99,7 +108,6 @@
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "warning",
"zone_has_empty_net": "error",
"zones_intersect": "error"
},
"rules": {
@ -107,20 +115,65 @@
"allow_microvias": false,
"max_error": 0.005,
"min_clearance": 0.0,
"min_connection": 0.0,
"min_copper_edge_clearance": 0.024999999999999998,
"min_hole_clearance": 0.0,
"min_hole_to_hole": 0.25,
"min_microvia_diameter": 0.19999999999999998,
"min_microvia_drill": 0.09999999999999999,
"min_resolved_spokes": 2,
"min_silk_clearance": 0.0,
"min_text_height": 0.7,
"min_text_thickness": 0.08,
"min_through_hole_diameter": 0.19999999999999998,
"min_track_width": 0.09999999999999999,
"min_via_annular_width": 0.049999999999999996,
"min_via_diameter": 0.44999999999999996,
"solder_mask_clearance": 0.0,
"solder_mask_min_width": 0.0,
"solder_mask_to_copper_clearance": 0.0,
"use_height_for_length_calcs": true
},
"teardrop_options": [
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 5,
"td_on_pad_in_zone": false,
"td_onpadsmd": true,
"td_onroundshapesonly": false,
"td_ontrackend": false,
"td_onviapad": true
}
],
"teardrop_parameters": [
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_round_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_rect_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_track_end",
"td_width_to_size_filter_ratio": 0.9
}
],
"track_widths": [
0.0,
0.1,
@ -147,7 +200,8 @@
"zones_allow_external_fillets": false,
"zones_use_no_outline": true
},
"layer_presets": []
"layer_presets": [],
"viewports": []
},
"boards": [],
"cvpcb": {
@ -331,18 +385,23 @@
"rule_severities": {
"bus_definition_conflict": "error",
"bus_entry_needed": "error",
"bus_label_syntax": "error",
"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"conflicting_netclasses": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_reference": "error",
"duplicate_sheet_names": "error",
"endpoint_off_grid": "warning",
"extra_units": "error",
"global_label_dangling": "warning",
"hier_label_mismatch": "error",
"label_dangling": "error",
"lib_symbol_issues": "warning",
"missing_bidi_pin": "warning",
"missing_input_pin": "warning",
"missing_power_pin": "error",
"missing_unit": "warning",
"multiple_net_names": "warning",
"net_not_bus_member": "warning",
"no_connect_connected": "warning",
@ -352,6 +411,7 @@
"pin_to_pin": "warning",
"power_pin_not_driven": "error",
"similar_labels": "warning",
"simulation_model_issue": "error",
"unannotated": "error",
"unit_value_mismatch": "error",
"unresolved_variable": "error",
@ -369,7 +429,7 @@
"net_settings": {
"classes": [
{
"bus_width": 12.0,
"bus_width": 12,
"clearance": 0.11,
"diff_pair_gap": 0.1,
"diff_pair_via_gap": 0.25,
@ -383,10 +443,10 @@
"track_width": 0.11,
"via_diameter": 0.45,
"via_drill": 0.2,
"wire_width": 6.0
"wire_width": 6
},
{
"bus_width": 12.0,
"bus_width": 12,
"clearance": 0.11,
"diff_pair_gap": 0.11,
"diff_pair_via_gap": 0.25,
@ -395,39 +455,15 @@
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "DP",
"nets": [
"/dp_in/DP0N",
"/dp_in/DP0P",
"/dp_in/DP1N",
"/dp_in/DP1P",
"/dp_in/DPAUXN",
"/dp_in/DPAUXP",
"/dp_in/RX1N",
"/dp_in/RX1NC",
"/dp_in/RX1P",
"/dp_in/RX1PC",
"/dp_in/RX2N",
"/dp_in/RX2NC",
"/dp_in/RX2P",
"/dp_in/RX2PC",
"/dp_in/TX1N",
"/dp_in/TX1NC",
"/dp_in/TX1P",
"/dp_in/TX1PC",
"/dp_in/TX2N",
"/dp_in/TX2NC",
"/dp_in/TX2P",
"/dp_in/TX2PC"
],
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.15,
"via_diameter": 0.45,
"via_drill": 0.2,
"wire_width": 6.0
"wire_width": 6
},
{
"bus_width": 12.0,
"bus_width": 12,
"clearance": 0.11,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
@ -436,59 +472,15 @@
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "EPD",
"nets": [
"/eink/ED0",
"/eink/ED1",
"/eink/ED10",
"/eink/ED11",
"/eink/ED12",
"/eink/ED13",
"/eink/ED14",
"/eink/ED15",
"/eink/ED2",
"/eink/ED3",
"/eink/ED4",
"/eink/ED5",
"/eink/ED6",
"/eink/ED7",
"/eink/ED8",
"/eink/ED9",
"/eink/ESDCLK",
"/eink/ESDLE",
"/eink/ESDOE",
"EPDC_D0",
"EPDC_D1",
"EPDC_D10",
"EPDC_D11",
"EPDC_D12",
"EPDC_D13",
"EPDC_D14",
"EPDC_D15",
"EPDC_D2",
"EPDC_D3",
"EPDC_D4",
"EPDC_D5",
"EPDC_D6",
"EPDC_D7",
"EPDC_D8",
"EPDC_D9",
"EPDC_GDCLK",
"EPDC_GDOE",
"EPDC_GDSP",
"EPDC_SDCE0",
"EPDC_SDCLK",
"EPDC_SDLE",
"EPDC_SDOE"
],
"pcb_color": "rgb(255, 0, 191)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.11,
"via_diameter": 0.45,
"via_drill": 0.2,
"wire_width": 6.0
"wire_width": 6
},
{
"bus_width": 12.0,
"bus_width": 12,
"clearance": 0.11,
"diff_pair_gap": 0.11,
"diff_pair_via_gap": 0.25,
@ -497,31 +489,15 @@
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "LVDS",
"nets": [
"LVDS_EVEN_AN",
"LVDS_EVEN_AP",
"LVDS_EVEN_BN",
"LVDS_EVEN_BP",
"LVDS_EVEN_CN",
"LVDS_EVEN_CP",
"LVDS_ODD_AN",
"LVDS_ODD_AP",
"LVDS_ODD_BN",
"LVDS_ODD_BP",
"LVDS_ODD_CKN",
"LVDS_ODD_CKP",
"LVDS_ODD_CN",
"LVDS_ODD_CP"
],
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.15,
"via_diameter": 0.45,
"via_drill": 0.2,
"wire_width": 6.0
"wire_width": 6
},
{
"bus_width": 12.0,
"bus_width": 12,
"clearance": 0.1,
"diff_pair_gap": 0.1,
"diff_pair_via_gap": 0.25,
@ -530,44 +506,15 @@
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "SDRAM_A",
"nets": [
"/fpga_ddr/DRAM_ADDR0",
"/fpga_ddr/DRAM_ADDR1",
"/fpga_ddr/DRAM_ADDR10",
"/fpga_ddr/DRAM_ADDR11",
"/fpga_ddr/DRAM_ADDR12",
"/fpga_ddr/DRAM_ADDR13",
"/fpga_ddr/DRAM_ADDR14",
"/fpga_ddr/DRAM_ADDR2",
"/fpga_ddr/DRAM_ADDR3",
"/fpga_ddr/DRAM_ADDR4",
"/fpga_ddr/DRAM_ADDR5",
"/fpga_ddr/DRAM_ADDR6",
"/fpga_ddr/DRAM_ADDR7",
"/fpga_ddr/DRAM_ADDR8",
"/fpga_ddr/DRAM_ADDR9",
"/fpga_ddr/DRAM_BA0",
"/fpga_ddr/DRAM_BA1",
"/fpga_ddr/DRAM_BA2",
"/fpga_ddr/DRAM_CASB",
"/fpga_ddr/DRAM_CKE",
"/fpga_ddr/DRAM_CKN",
"/fpga_ddr/DRAM_CKP",
"/fpga_ddr/DRAM_CSB",
"/fpga_ddr/DRAM_ODT",
"/fpga_ddr/DRAM_RASB",
"/fpga_ddr/DRAM_RST",
"/fpga_ddr/DRAM_WEB"
],
"pcb_color": "rgb(103, 255, 0)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.1,
"via_diameter": 0.45,
"via_drill": 0.2,
"wire_width": 6.0
"wire_width": 6
},
{
"bus_width": 12.0,
"bus_width": 12,
"clearance": 0.1,
"diff_pair_gap": 0.1,
"diff_pair_via_gap": 0.25,
@ -576,28 +523,15 @@
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "SDRAM_H",
"nets": [
"/fpga_ddr/DRAM_DATA10",
"/fpga_ddr/DRAM_DATA11",
"/fpga_ddr/DRAM_DATA12",
"/fpga_ddr/DRAM_DATA13",
"/fpga_ddr/DRAM_DATA14",
"/fpga_ddr/DRAM_DATA15",
"/fpga_ddr/DRAM_DATA8",
"/fpga_ddr/DRAM_DATA9",
"/fpga_ddr/DRAM_UDM",
"/fpga_ddr/DRAM_UDQSN",
"/fpga_ddr/DRAM_UDQSP"
],
"pcb_color": "rgb(255, 252, 0)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.1,
"via_diameter": 0.45,
"via_drill": 0.2,
"wire_width": 6.0
"wire_width": 6
},
{
"bus_width": 12.0,
"bus_width": 12,
"clearance": 0.1,
"diff_pair_gap": 0.1,
"diff_pair_via_gap": 0.25,
@ -606,28 +540,15 @@
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "SDRAM_L",
"nets": [
"/fpga_ddr/DRAM_DATA0",
"/fpga_ddr/DRAM_DATA1",
"/fpga_ddr/DRAM_DATA2",
"/fpga_ddr/DRAM_DATA3",
"/fpga_ddr/DRAM_DATA4",
"/fpga_ddr/DRAM_DATA5",
"/fpga_ddr/DRAM_DATA6",
"/fpga_ddr/DRAM_DATA7",
"/fpga_ddr/DRAM_LDM",
"/fpga_ddr/DRAM_LDQSN",
"/fpga_ddr/DRAM_LDQSP"
],
"pcb_color": "rgb(255, 131, 3)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.1,
"via_diameter": 0.45,
"via_drill": 0.2,
"wire_width": 6.0
"wire_width": 6
},
{
"bus_width": 12.0,
"bus_width": 12,
"clearance": 0.11,
"diff_pair_gap": 0.11,
"diff_pair_via_gap": 0.25,
@ -636,17 +557,16 @@
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "USB",
"nets": [],
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.15,
"via_diameter": 0.45,
"via_drill": 0.2,
"wire_width": 6.0
"wire_width": 6
}
],
"meta": {
"version": 2
"version": 3
},
"net_colors": {
"+1V1": "rgb(255, 92, 56)",
@ -654,7 +574,518 @@
"+3V3": "rgb(179, 228, 50)",
"+5V": "rgb(255, 122, 107)",
"GND": "rgb(0, 94, 255)"
}
},
"netclass_assignments": null,
"netclass_patterns": [
{
"netclass": "DP",
"pattern": "/dp_in/DP0N"
},
{
"netclass": "DP",
"pattern": "/dp_in/DP0P"
},
{
"netclass": "DP",
"pattern": "/dp_in/DP1N"
},
{
"netclass": "DP",
"pattern": "/dp_in/DP1P"
},
{
"netclass": "DP",
"pattern": "/dp_in/DPAUXN"
},
{
"netclass": "DP",
"pattern": "/dp_in/DPAUXP"
},
{
"netclass": "DP",
"pattern": "/dp_in/RX1N"
},
{
"netclass": "DP",
"pattern": "/dp_in/RX1NC"
},
{
"netclass": "DP",
"pattern": "/dp_in/RX1P"
},
{
"netclass": "DP",
"pattern": "/dp_in/RX1PC"
},
{
"netclass": "DP",
"pattern": "/dp_in/RX2N"
},
{
"netclass": "DP",
"pattern": "/dp_in/RX2NC"
},
{
"netclass": "DP",
"pattern": "/dp_in/RX2P"
},
{
"netclass": "DP",
"pattern": "/dp_in/RX2PC"
},
{
"netclass": "DP",
"pattern": "/dp_in/TX1N"
},
{
"netclass": "DP",
"pattern": "/dp_in/TX1NC"
},
{
"netclass": "DP",
"pattern": "/dp_in/TX1P"
},
{
"netclass": "DP",
"pattern": "/dp_in/TX1PC"
},
{
"netclass": "DP",
"pattern": "/dp_in/TX2N"
},
{
"netclass": "DP",
"pattern": "/dp_in/TX2NC"
},
{
"netclass": "DP",
"pattern": "/dp_in/TX2P"
},
{
"netclass": "DP",
"pattern": "/dp_in/TX2PC"
},
{
"netclass": "EPD",
"pattern": "/eink/ED0"
},
{
"netclass": "EPD",
"pattern": "/eink/ED1"
},
{
"netclass": "EPD",
"pattern": "/eink/ED10"
},
{
"netclass": "EPD",
"pattern": "/eink/ED11"
},
{
"netclass": "EPD",
"pattern": "/eink/ED12"
},
{
"netclass": "EPD",
"pattern": "/eink/ED13"
},
{
"netclass": "EPD",
"pattern": "/eink/ED14"
},
{
"netclass": "EPD",
"pattern": "/eink/ED15"
},
{
"netclass": "EPD",
"pattern": "/eink/ED2"
},
{
"netclass": "EPD",
"pattern": "/eink/ED3"
},
{
"netclass": "EPD",
"pattern": "/eink/ED4"
},
{
"netclass": "EPD",
"pattern": "/eink/ED5"
},
{
"netclass": "EPD",
"pattern": "/eink/ED6"
},
{
"netclass": "EPD",
"pattern": "/eink/ED7"
},
{
"netclass": "EPD",
"pattern": "/eink/ED8"
},
{
"netclass": "EPD",
"pattern": "/eink/ED9"
},
{
"netclass": "EPD",
"pattern": "/eink/ESDCLK"
},
{
"netclass": "EPD",
"pattern": "/eink/ESDLE"
},
{
"netclass": "EPD",
"pattern": "/eink/ESDOE"
},
{
"netclass": "EPD",
"pattern": "EPDC_D0"
},
{
"netclass": "EPD",
"pattern": "EPDC_D1"
},
{
"netclass": "EPD",
"pattern": "EPDC_D10"
},
{
"netclass": "EPD",
"pattern": "EPDC_D11"
},
{
"netclass": "EPD",
"pattern": "EPDC_D12"
},
{
"netclass": "EPD",
"pattern": "EPDC_D13"
},
{
"netclass": "EPD",
"pattern": "EPDC_D14"
},
{
"netclass": "EPD",
"pattern": "EPDC_D15"
},
{
"netclass": "EPD",
"pattern": "EPDC_D2"
},
{
"netclass": "EPD",
"pattern": "EPDC_D3"
},
{
"netclass": "EPD",
"pattern": "EPDC_D4"
},
{
"netclass": "EPD",
"pattern": "EPDC_D5"
},
{
"netclass": "EPD",
"pattern": "EPDC_D6"
},
{
"netclass": "EPD",
"pattern": "EPDC_D7"
},
{
"netclass": "EPD",
"pattern": "EPDC_D8"
},
{
"netclass": "EPD",
"pattern": "EPDC_D9"
},
{
"netclass": "EPD",
"pattern": "EPDC_GDCLK"
},
{
"netclass": "EPD",
"pattern": "EPDC_GDOE"
},
{
"netclass": "EPD",
"pattern": "EPDC_GDSP"
},
{
"netclass": "EPD",
"pattern": "EPDC_SDCE0"
},
{
"netclass": "EPD",
"pattern": "EPDC_SDCLK"
},
{
"netclass": "EPD",
"pattern": "EPDC_SDLE"
},
{
"netclass": "EPD",
"pattern": "EPDC_SDOE"
},
{
"netclass": "LVDS",
"pattern": "LVDS_EVEN_AN"
},
{
"netclass": "LVDS",
"pattern": "LVDS_EVEN_AP"
},
{
"netclass": "LVDS",
"pattern": "LVDS_EVEN_BN"
},
{
"netclass": "LVDS",
"pattern": "LVDS_EVEN_BP"
},
{
"netclass": "LVDS",
"pattern": "LVDS_EVEN_CN"
},
{
"netclass": "LVDS",
"pattern": "LVDS_EVEN_CP"
},
{
"netclass": "LVDS",
"pattern": "LVDS_ODD_AN"
},
{
"netclass": "LVDS",
"pattern": "LVDS_ODD_AP"
},
{
"netclass": "LVDS",
"pattern": "LVDS_ODD_BN"
},
{
"netclass": "LVDS",
"pattern": "LVDS_ODD_BP"
},
{
"netclass": "LVDS",
"pattern": "LVDS_ODD_CKN"
},
{
"netclass": "LVDS",
"pattern": "LVDS_ODD_CKP"
},
{
"netclass": "LVDS",
"pattern": "LVDS_ODD_CN"
},
{
"netclass": "LVDS",
"pattern": "LVDS_ODD_CP"
},
{
"netclass": "SDRAM_A",
"pattern": "/fpga_ddr/DRAM_ADDR0"
},
{
"netclass": "SDRAM_A",
"pattern": "/fpga_ddr/DRAM_ADDR1"
},
{
"netclass": "SDRAM_A",
"pattern": "/fpga_ddr/DRAM_ADDR10"
},
{
"netclass": "SDRAM_A",
"pattern": "/fpga_ddr/DRAM_ADDR11"
},
{
"netclass": "SDRAM_A",
"pattern": "/fpga_ddr/DRAM_ADDR12"
},
{
"netclass": "SDRAM_A",
"pattern": "/fpga_ddr/DRAM_ADDR13"
},
{
"netclass": "SDRAM_A",
"pattern": "/fpga_ddr/DRAM_ADDR14"
},
{
"netclass": "SDRAM_A",
"pattern": "/fpga_ddr/DRAM_ADDR2"
},
{
"netclass": "SDRAM_A",
"pattern": "/fpga_ddr/DRAM_ADDR3"
},
{
"netclass": "SDRAM_A",
"pattern": "/fpga_ddr/DRAM_ADDR4"
},
{
"netclass": "SDRAM_A",
"pattern": "/fpga_ddr/DRAM_ADDR5"
},
{
"netclass": "SDRAM_A",
"pattern": "/fpga_ddr/DRAM_ADDR6"
},
{
"netclass": "SDRAM_A",
"pattern": "/fpga_ddr/DRAM_ADDR7"
},
{
"netclass": "SDRAM_A",
"pattern": "/fpga_ddr/DRAM_ADDR8"
},
{
"netclass": "SDRAM_A",
"pattern": "/fpga_ddr/DRAM_ADDR9"
},
{
"netclass": "SDRAM_A",
"pattern": "/fpga_ddr/DRAM_BA0"
},
{
"netclass": "SDRAM_A",
"pattern": "/fpga_ddr/DRAM_BA1"
},
{
"netclass": "SDRAM_A",
"pattern": "/fpga_ddr/DRAM_BA2"
},
{
"netclass": "SDRAM_A",
"pattern": "/fpga_ddr/DRAM_CASB"
},
{
"netclass": "SDRAM_A",
"pattern": "/fpga_ddr/DRAM_CKE"
},
{
"netclass": "SDRAM_A",
"pattern": "/fpga_ddr/DRAM_CKN"
},
{
"netclass": "SDRAM_A",
"pattern": "/fpga_ddr/DRAM_CKP"
},
{
"netclass": "SDRAM_A",
"pattern": "/fpga_ddr/DRAM_CSB"
},
{
"netclass": "SDRAM_A",
"pattern": "/fpga_ddr/DRAM_ODT"
},
{
"netclass": "SDRAM_A",
"pattern": "/fpga_ddr/DRAM_RASB"
},
{
"netclass": "SDRAM_A",
"pattern": "/fpga_ddr/DRAM_RST"
},
{
"netclass": "SDRAM_A",
"pattern": "/fpga_ddr/DRAM_WEB"
},
{
"netclass": "SDRAM_H",
"pattern": "/fpga_ddr/DRAM_DATA10"
},
{
"netclass": "SDRAM_H",
"pattern": "/fpga_ddr/DRAM_DATA11"
},
{
"netclass": "SDRAM_H",
"pattern": "/fpga_ddr/DRAM_DATA12"
},
{
"netclass": "SDRAM_H",
"pattern": "/fpga_ddr/DRAM_DATA13"
},
{
"netclass": "SDRAM_H",
"pattern": "/fpga_ddr/DRAM_DATA14"
},
{
"netclass": "SDRAM_H",
"pattern": "/fpga_ddr/DRAM_DATA15"
},
{
"netclass": "SDRAM_H",
"pattern": "/fpga_ddr/DRAM_DATA8"
},
{
"netclass": "SDRAM_H",
"pattern": "/fpga_ddr/DRAM_DATA9"
},
{
"netclass": "SDRAM_H",
"pattern": "/fpga_ddr/DRAM_UDM"
},
{
"netclass": "SDRAM_H",
"pattern": "/fpga_ddr/DRAM_UDQSN"
},
{
"netclass": "SDRAM_H",
"pattern": "/fpga_ddr/DRAM_UDQSP"
},
{
"netclass": "SDRAM_L",
"pattern": "/fpga_ddr/DRAM_DATA0"
},
{
"netclass": "SDRAM_L",
"pattern": "/fpga_ddr/DRAM_DATA1"
},
{
"netclass": "SDRAM_L",
"pattern": "/fpga_ddr/DRAM_DATA2"
},
{
"netclass": "SDRAM_L",
"pattern": "/fpga_ddr/DRAM_DATA3"
},
{
"netclass": "SDRAM_L",
"pattern": "/fpga_ddr/DRAM_DATA4"
},
{
"netclass": "SDRAM_L",
"pattern": "/fpga_ddr/DRAM_DATA5"
},
{
"netclass": "SDRAM_L",
"pattern": "/fpga_ddr/DRAM_DATA6"
},
{
"netclass": "SDRAM_L",
"pattern": "/fpga_ddr/DRAM_DATA7"
},
{
"netclass": "SDRAM_L",
"pattern": "/fpga_ddr/DRAM_LDM"
},
{
"netclass": "SDRAM_L",
"pattern": "/fpga_ddr/DRAM_LDQSN"
},
{
"netclass": "SDRAM_L",
"pattern": "/fpga_ddr/DRAM_LDQSP"
}
]
},
"pcbnew": {
"last_paths": {
@ -670,6 +1101,8 @@
"schematic": {
"annotate_start_num": 400,
"drawing": {
"dashed_lines_dash_length_ratio": 12.0,
"dashed_lines_gap_length_ratio": 3.0,
"default_bus_thickness": 12.0,
"default_line_thickness": 6.0,
"default_text_size": 50.0,
@ -703,7 +1136,11 @@
"page_layout_descr_file": "",
"plot_directory": "./",
"spice_adjust_passive_values": false,
"spice_current_sheet_as_root": false,
"spice_external_command": "spice \"%I\"",
"spice_model_current_sheet_as_root": true,
"spice_save_all_currents": false,
"spice_save_all_voltages": false,
"subpart_first_id": 65,
"subpart_id_separator": 0
},

1109
pcb/mainboard/pcb.kicad_sch
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2362
pcb/mainboard/power.kicad_sch
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