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Initial design of lite version
This commit is contained in:
parent
0b6dba5c83
commit
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14 changed files with 69441 additions and 1287 deletions
114
pcb/common/footprints.pretty/BGA-60_9x10_10.0x11.5mm.kicad_mod
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114
pcb/common/footprints.pretty/BGA-60_9x10_10.0x11.5mm.kicad_mod
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(footprint "BGA-60_9x10_10.0x11.5mm" (version 20221018) (generator pcbnew)
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(layer "F.Cu")
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(attr smd)
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(fp_text reference "REF**" (at 0 -6.75) (layer "F.SilkS")
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(effects (font (size 1 1) (thickness 0.15)))
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(tstamp 6ef97399-2538-46b2-b406-b6fdb6d53873)
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)
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(fp_text value "BGA-60_9x10_10.0x11.5mm" (at 0 6.75) (layer "F.Fab")
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(effects (font (size 1 1) (thickness 0.15)))
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(tstamp 51e3cfc1-3a23-41a5-83cb-932f5c72c4ff)
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)
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(fp_text user "${REFERENCE}" (at 0 0) (layer "F.Fab")
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(effects (font (size 1 1) (thickness 0.15)))
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(tstamp 898197a2-6be2-4dc9-afc8-e816cc16c100)
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)
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(fp_line (start -5.12 -4.75) (end -5.12 -2.995)
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(stroke (width 0.12) (type default)) (layer "F.SilkS") (tstamp c4d72759-f9cf-4778-80bf-d68945d849a0))
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||||||
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(fp_line (start -5.12 5.87) (end -5.12 2.995)
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||||||
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(stroke (width 0.12) (type default)) (layer "F.SilkS") (tstamp 16d70370-30d3-4b64-82f7-9918aa47c4e4))
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||||||
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(fp_line (start -4 -5.87) (end -5.12 -4.75)
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||||||
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(stroke (width 0.12) (type default)) (layer "F.SilkS") (tstamp 02512a7e-3a7a-4ee4-81b8-496d97c178bb))
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||||||
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(fp_line (start -2.62 -5.87) (end -4 -5.87)
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||||||
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(stroke (width 0.12) (type default)) (layer "F.SilkS") (tstamp 3c4ee0ad-c310-4c32-9c31-607bed6f995b))
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||||||
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(fp_line (start -2.62 5.87) (end -5.12 5.87)
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||||||
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(stroke (width 0.12) (type default)) (layer "F.SilkS") (tstamp ef23cf85-fa98-4b19-b5f4-701fa3f9c8d9))
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||||||
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(fp_line (start 2.62 -5.87) (end 5.12 -5.87)
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||||||
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(stroke (width 0.12) (type default)) (layer "F.SilkS") (tstamp bb26f7ef-3633-4ffd-bcd9-b090dd0d3a4c))
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(fp_line (start 2.62 5.87) (end 5.12 5.87)
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||||||
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(stroke (width 0.12) (type default)) (layer "F.SilkS") (tstamp e76a3762-359e-4770-92a7-c713c4e8ec52))
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(fp_line (start 5.12 -5.87) (end 5.12 -2.995)
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(stroke (width 0.12) (type default)) (layer "F.SilkS") (tstamp 2c11485c-ff09-4f01-8167-965707924caa))
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(fp_line (start 5.12 5.87) (end 5.12 2.995)
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(stroke (width 0.12) (type default)) (layer "F.SilkS") (tstamp 872cac61-d4c6-42e9-b042-18274bc7287f))
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(fp_circle (center -5 -5.75) (end -5 -5.65)
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(stroke (width 0.2) (type default)) (fill none) (layer "F.SilkS") (tstamp 9ff6722b-2490-4f81-980c-b5d29bd9d9d2))
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(fp_line (start -5.25 -6) (end 5.25 -6)
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(stroke (width 0.05) (type default)) (layer "F.CrtYd") (tstamp c9d83a81-a2f2-4138-9a46-8a7ca964f7ab))
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(fp_line (start -5.25 6) (end -5.25 -6)
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(stroke (width 0.05) (type default)) (layer "F.CrtYd") (tstamp 9be05e98-d3af-4c15-81db-a97a505bcd90))
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(fp_line (start 5.25 -6) (end 5.25 6)
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(stroke (width 0.05) (type default)) (layer "F.CrtYd") (tstamp 72716308-00e0-465a-a638-9d7adac155ec))
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(fp_line (start 5.25 6) (end -5.25 6)
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(stroke (width 0.05) (type default)) (layer "F.CrtYd") (tstamp b583fbc6-0ab1-4586-9f98-a6ef191c0f2e))
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(fp_line (start -5 -4.75) (end -5 5.75)
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(stroke (width 0.1) (type default)) (layer "F.Fab") (tstamp 9421e41b-d7ad-4c17-84e4-afaafc1e002d))
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(fp_line (start -5 5.75) (end 5 5.75)
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(stroke (width 0.1) (type default)) (layer "F.Fab") (tstamp 2593df18-42c2-40c7-aca6-01ee7f61ddd5))
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||||||
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(fp_line (start -4 -5.75) (end -5 -4.75)
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(stroke (width 0.1) (type default)) (layer "F.Fab") (tstamp 04f8ce39-9eac-4d69-903a-68509060be13))
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(fp_line (start 5 -5.75) (end -4 -5.75)
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(stroke (width 0.1) (type default)) (layer "F.Fab") (tstamp 4aa3af0d-4ebb-4144-8c62-8228d582675c))
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(fp_line (start 5 5.75) (end 5 -5.75)
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(stroke (width 0.1) (type default)) (layer "F.Fab") (tstamp 34191f04-7f94-4cb4-8243-15cbda571e2a))
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(pad "A1" smd circle (at -3.2 -3.6) (size 0.4 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 1ed8e2fb-597a-4dd5-9c1a-e0822425530c))
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(pad "A2" smd circle (at -2.4 -3.6) (size 0.4 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp f1f03b20-cd15-4783-b1ce-1f0d3495feea))
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(pad "A3" smd circle (at -1.6 -3.6) (size 0.4 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp e7a7f501-0ef3-47d6-bd04-1f9d1609df86))
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(pad "A7" smd circle (at 1.6 -3.6) (size 0.4 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 68bbd399-8f19-4dbe-8e0c-cb5e1c29ce68))
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(pad "A8" smd circle (at 2.4 -3.6) (size 0.4 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 94f005b6-29db-4e51-8625-c4703ccdd19a))
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(pad "A9" smd circle (at 3.2 -3.6) (size 0.4 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 082c0a61-7608-469a-8d61-1cf8234cbb06))
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(pad "B1" smd circle (at -3.2 -2.8) (size 0.4 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp def8dc9a-6912-4463-9bae-472409b0d1c3))
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(pad "B2" smd circle (at -2.4 -2.8) (size 0.4 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp fa9a142c-cfe6-4423-aef2-cf5b5b5f2a02))
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(pad "B3" smd circle (at -1.6 -2.8) (size 0.4 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp bcdc01f7-0971-4016-bf91-5128a9c514bd))
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(pad "B7" smd circle (at 1.6 -2.8) (size 0.4 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 83df7a60-8830-472e-9f48-9d8921ca9f32))
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(pad "B8" smd circle (at 2.4 -2.8) (size 0.4 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp f8961775-ed36-4ecf-b5ab-903d962e30a5))
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(pad "B9" smd circle (at 3.2 -2.8) (size 0.4 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp f0c2e495-b659-4fc1-98a4-21e8d1732dce))
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(pad "C1" smd circle (at -3.2 -2) (size 0.4 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 392eb024-581a-451b-bcb1-8f1d0f5c957d))
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(pad "C2" smd circle (at -2.4 -2) (size 0.4 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp ac1d9d5e-219c-409a-a31d-ed4910b886f2))
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(pad "C3" smd circle (at -1.6 -2) (size 0.4 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 5246e2b3-ed55-4f30-b96f-2be7564dc700))
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(pad "C7" smd circle (at 1.6 -2) (size 0.4 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp b9747526-ce81-4294-8638-4a8fcdb676f6))
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(pad "C8" smd circle (at 2.4 -2) (size 0.4 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 94248dbc-3a0a-46da-bf80-550e4b8890cd))
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(pad "C9" smd circle (at 3.2 -2) (size 0.4 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp bfcc721a-9661-4a80-9401-7828ab1c91d3))
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(pad "D1" smd circle (at -3.2 -1.2) (size 0.4 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp ec01fb19-059b-4d1d-a4df-db7cbdb48e7f))
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(pad "D2" smd circle (at -2.4 -1.2) (size 0.4 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp d53cfca3-18c9-4c95-95da-125f8da9ff9b))
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(pad "D3" smd circle (at -1.6 -1.2) (size 0.4 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 10c0ed62-ed0b-4798-91ae-54ccea753569))
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(pad "D7" smd circle (at 1.6 -1.2) (size 0.4 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 34e43709-fcad-489a-b355-e50523b60062))
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(pad "D8" smd circle (at 2.4 -1.2) (size 0.4 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp a6034dc0-8305-4289-8506-d7c9f57691e5))
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(pad "D9" smd circle (at 3.2 -1.2) (size 0.4 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 3e122192-1295-4aa8-97e5-8fe727d0ee60))
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(pad "E1" smd circle (at -3.2 -0.4) (size 0.4 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp e7c8456b-af20-465d-8c5f-f9870396d2ab))
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(pad "E2" smd circle (at -2.4 -0.4) (size 0.4 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp a1fb7f28-36ea-4590-945a-9ad008a37b28))
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(pad "E3" smd circle (at -1.6 -0.4) (size 0.4 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 53520db0-46e1-4ac6-b905-699bc241924b))
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(pad "E7" smd circle (at 1.6 -0.4) (size 0.4 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp a103d333-2b65-450a-8cdc-10e1da599fd1))
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(pad "E8" smd circle (at 2.4 -0.4) (size 0.4 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 2b07ced1-40b8-464f-9aa3-23fc4ffedd27))
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(pad "E9" smd circle (at 3.2 -0.4) (size 0.4 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp be201012-ccf5-4765-af9f-1d00193db717))
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(pad "F1" smd circle (at -3.2 0.4) (size 0.4 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 4213c3c9-2f4b-49d9-ad21-b29ab90a5d5e))
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(pad "F2" smd circle (at -2.4 0.4) (size 0.4 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp ca10451a-e061-407d-a677-315ef3de80e3))
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(pad "F3" smd circle (at -1.6 0.4) (size 0.4 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 59146dbb-e324-42f4-8eb7-9f071cee14b1))
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(pad "F7" smd circle (at 1.6 0.4) (size 0.4 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp c4067c59-f6b6-4711-bd56-227a56cc770c))
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(pad "F8" smd circle (at 2.4 0.4) (size 0.4 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp b47558d7-c796-411f-856f-0bf42482b186))
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(pad "F9" smd circle (at 3.2 0.4) (size 0.4 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp dde6347b-62b1-40f0-9e1e-446581d960bb))
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(pad "G1" smd circle (at -3.2 1.2) (size 0.4 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp a03ce8f8-ec84-453f-adc2-aeecaae0afb0))
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(pad "G2" smd circle (at -2.4 1.2) (size 0.4 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp ef6d9358-78ac-48c6-b945-6e81a0764a53))
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(pad "G3" smd circle (at -1.6 1.2) (size 0.4 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 8e95f3ac-9d7c-472f-8fcb-6530be3fa0c8))
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(pad "G7" smd circle (at 1.6 1.2) (size 0.4 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 540cc0d3-25c5-499b-ac56-59e7e777ebbb))
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(pad "G8" smd circle (at 2.4 1.2) (size 0.4 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 3e8d9619-ad2c-4e26-b30c-113efd6ea3e9))
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(pad "G9" smd circle (at 3.2 1.2) (size 0.4 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp c20c2f77-c6f3-410b-882e-c91061a9b6dc))
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(pad "H1" smd circle (at -3.2 2) (size 0.4 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp acf3d1cb-86a5-4026-aa3c-cf1b67f376e1))
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(pad "H2" smd circle (at -2.4 2) (size 0.4 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 2e5cfbbf-dbbf-47a8-a26c-e7487da00e71))
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(pad "H3" smd circle (at -1.6 2) (size 0.4 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 95041607-6113-4ec7-ada0-a291ade51cf3))
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(pad "H7" smd circle (at 1.6 2) (size 0.4 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp d0004639-c663-4017-858d-83b964d4a24e))
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(pad "H8" smd circle (at 2.4 2) (size 0.4 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 7c337360-91d4-42ac-9e82-2ab75e0733b8))
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(pad "H9" smd circle (at 3.2 2) (size 0.4 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp f3f03a7e-69ad-4986-b637-95f1d74877b0))
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(pad "J1" smd circle (at -3.2 2.8) (size 0.4 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp fee98fe8-de5c-49ca-8632-ae4dd4e566bc))
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(pad "J2" smd circle (at -2.4 2.8) (size 0.4 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp ea39c172-c047-442d-b459-762b490c1a54))
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(pad "J3" smd circle (at -1.6 2.8) (size 0.4 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 021d163a-c307-4d36-bf26-dbe11c3d80d1))
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(pad "J7" smd circle (at 1.6 2.8) (size 0.4 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 58350fd9-8875-4845-93ed-3df4d1e6c985))
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(pad "J8" smd circle (at 2.4 2.8) (size 0.4 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 12db921e-f783-4d8a-b292-36fab0d15107))
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(pad "J9" smd circle (at 3.2 2.8) (size 0.4 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp c93e99db-de08-4966-8296-b8c02b264bad))
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(pad "K1" smd circle (at -3.2 3.6) (size 0.4 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp bd4c8ead-25e4-4cb5-acda-ef0f09ba28a4))
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(pad "K2" smd circle (at -2.4 3.6) (size 0.4 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp d35221d4-53af-4ba7-a180-1eadcce69977))
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(pad "K3" smd circle (at -1.6 3.6) (size 0.4 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp e7287c5b-eaab-4eb5-8fe3-4b4581b74cd2))
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(pad "K7" smd circle (at 1.6 3.6) (size 0.4 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp af4de8dc-74df-4303-9125-f59b97dbf82b))
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(pad "K8" smd circle (at 2.4 3.6) (size 0.4 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 7832a5d8-ba3e-406a-9dfa-82bca01f816d))
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(pad "K9" smd circle (at 3.2 3.6) (size 0.4 0.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 52b0748c-7f27-46aa-99c1-e6f99932399d))
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)
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pcb/mainboard_lite/dp_in.kicad_sch
Normal file
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pcb/mainboard_lite/dp_in.kicad_sch
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pcb/mainboard_lite/eink.kicad_sch
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pcb/mainboard_lite/eink.kicad_sch
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pcb/mainboard_lite/fp-info-cache
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pcb/mainboard_lite/fp-info-cache
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pcb/mainboard_lite/fp-lib-table
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pcb/mainboard_lite/fp-lib-table
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(fp_lib_table
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(lib (name "footprints")(type "KiCad")(uri "${KIPRJMOD}/../common/footprints.pretty")(options "")(descr ""))
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)
|
3987
pcb/mainboard_lite/fpga.kicad_sch
Normal file
3987
pcb/mainboard_lite/fpga.kicad_sch
Normal file
File diff suppressed because it is too large
Load diff
5273
pcb/mainboard_lite/fpga_ddr.kicad_sch
Normal file
5273
pcb/mainboard_lite/fpga_ddr.kicad_sch
Normal file
File diff suppressed because it is too large
Load diff
38813
pcb/mainboard_lite/pcb.kicad_pcb
Normal file
38813
pcb/mainboard_lite/pcb.kicad_pcb
Normal file
File diff suppressed because it is too large
Load diff
77
pcb/mainboard_lite/pcb.kicad_prl
Executable file
77
pcb/mainboard_lite/pcb.kicad_prl
Executable file
|
@ -0,0 +1,77 @@
|
||||||
|
{
|
||||||
|
"board": {
|
||||||
|
"active_layer": 0,
|
||||||
|
"active_layer_preset": "",
|
||||||
|
"auto_track_width": false,
|
||||||
|
"hidden_netclasses": [],
|
||||||
|
"hidden_nets": [],
|
||||||
|
"high_contrast_mode": 0,
|
||||||
|
"net_color_mode": 1,
|
||||||
|
"opacity": {
|
||||||
|
"images": 0.6,
|
||||||
|
"pads": 1.0,
|
||||||
|
"tracks": 1.0,
|
||||||
|
"vias": 1.0,
|
||||||
|
"zones": 1.0
|
||||||
|
},
|
||||||
|
"ratsnest_display_mode": 0,
|
||||||
|
"selection_filter": {
|
||||||
|
"dimensions": false,
|
||||||
|
"footprints": false,
|
||||||
|
"graphics": false,
|
||||||
|
"keepouts": false,
|
||||||
|
"lockedItems": true,
|
||||||
|
"otherItems": false,
|
||||||
|
"pads": false,
|
||||||
|
"text": true,
|
||||||
|
"tracks": false,
|
||||||
|
"vias": false,
|
||||||
|
"zones": false
|
||||||
|
},
|
||||||
|
"visible_items": [
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
2,
|
||||||
|
3,
|
||||||
|
4,
|
||||||
|
5,
|
||||||
|
8,
|
||||||
|
9,
|
||||||
|
10,
|
||||||
|
11,
|
||||||
|
12,
|
||||||
|
13,
|
||||||
|
14,
|
||||||
|
15,
|
||||||
|
16,
|
||||||
|
17,
|
||||||
|
18,
|
||||||
|
19,
|
||||||
|
20,
|
||||||
|
21,
|
||||||
|
22,
|
||||||
|
23,
|
||||||
|
24,
|
||||||
|
25,
|
||||||
|
26,
|
||||||
|
27,
|
||||||
|
28,
|
||||||
|
29,
|
||||||
|
30,
|
||||||
|
32,
|
||||||
|
33,
|
||||||
|
34,
|
||||||
|
35,
|
||||||
|
36
|
||||||
|
],
|
||||||
|
"visible_layers": "ffcffef_fffffff9",
|
||||||
|
"zone_display_mode": 0
|
||||||
|
},
|
||||||
|
"meta": {
|
||||||
|
"filename": "pcb.kicad_prl",
|
||||||
|
"version": 3
|
||||||
|
},
|
||||||
|
"project": {
|
||||||
|
"files": []
|
||||||
|
}
|
||||||
|
}
|
688
pcb/mainboard_lite/pcb.kicad_pro
Executable file
688
pcb/mainboard_lite/pcb.kicad_pro
Executable file
|
@ -0,0 +1,688 @@
|
||||||
|
{
|
||||||
|
"board": {
|
||||||
|
"3dviewports": [],
|
||||||
|
"design_settings": {
|
||||||
|
"defaults": {
|
||||||
|
"board_outline_line_width": 0.049999999999999996,
|
||||||
|
"copper_line_width": 0.19999999999999998,
|
||||||
|
"copper_text_italic": false,
|
||||||
|
"copper_text_size_h": 1.5,
|
||||||
|
"copper_text_size_v": 1.5,
|
||||||
|
"copper_text_thickness": 0.3,
|
||||||
|
"copper_text_upright": false,
|
||||||
|
"courtyard_line_width": 0.049999999999999996,
|
||||||
|
"dimension_precision": 4,
|
||||||
|
"dimension_units": 3,
|
||||||
|
"dimensions": {
|
||||||
|
"arrow_length": 1270000,
|
||||||
|
"extension_offset": 500000,
|
||||||
|
"keep_text_aligned": true,
|
||||||
|
"suppress_zeroes": false,
|
||||||
|
"text_position": 0,
|
||||||
|
"units_format": 1
|
||||||
|
},
|
||||||
|
"fab_line_width": 0.09999999999999999,
|
||||||
|
"fab_text_italic": false,
|
||||||
|
"fab_text_size_h": 1.0,
|
||||||
|
"fab_text_size_v": 1.0,
|
||||||
|
"fab_text_thickness": 0.15,
|
||||||
|
"fab_text_upright": false,
|
||||||
|
"other_line_width": 0.09999999999999999,
|
||||||
|
"other_text_italic": false,
|
||||||
|
"other_text_size_h": 1.0,
|
||||||
|
"other_text_size_v": 1.0,
|
||||||
|
"other_text_thickness": 0.15,
|
||||||
|
"other_text_upright": false,
|
||||||
|
"pads": {
|
||||||
|
"drill": 0.762,
|
||||||
|
"height": 1.524,
|
||||||
|
"width": 1.524
|
||||||
|
},
|
||||||
|
"silk_line_width": 0.12,
|
||||||
|
"silk_text_italic": false,
|
||||||
|
"silk_text_size_h": 0.7,
|
||||||
|
"silk_text_size_v": 0.7,
|
||||||
|
"silk_text_thickness": 0.09999999999999999,
|
||||||
|
"silk_text_upright": false,
|
||||||
|
"zones": {
|
||||||
|
"45_degree_only": false,
|
||||||
|
"min_clearance": 0.11
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"diff_pair_dimensions": [
|
||||||
|
{
|
||||||
|
"gap": 0.0,
|
||||||
|
"via_gap": 0.0,
|
||||||
|
"width": 0.0
|
||||||
|
}
|
||||||
|
],
|
||||||
|
"drc_exclusions": [],
|
||||||
|
"meta": {
|
||||||
|
"version": 2
|
||||||
|
},
|
||||||
|
"rule_severities": {
|
||||||
|
"annular_width": "error",
|
||||||
|
"clearance": "error",
|
||||||
|
"connection_width": "warning",
|
||||||
|
"copper_edge_clearance": "error",
|
||||||
|
"copper_sliver": "warning",
|
||||||
|
"courtyards_overlap": "warning",
|
||||||
|
"diff_pair_gap_out_of_range": "error",
|
||||||
|
"diff_pair_uncoupled_length_too_long": "error",
|
||||||
|
"drill_out_of_range": "error",
|
||||||
|
"duplicate_footprints": "warning",
|
||||||
|
"extra_footprint": "warning",
|
||||||
|
"footprint": "error",
|
||||||
|
"footprint_type_mismatch": "error",
|
||||||
|
"hole_clearance": "error",
|
||||||
|
"hole_near_hole": "error",
|
||||||
|
"invalid_outline": "error",
|
||||||
|
"isolated_copper": "warning",
|
||||||
|
"item_on_disabled_layer": "error",
|
||||||
|
"items_not_allowed": "error",
|
||||||
|
"length_out_of_range": "error",
|
||||||
|
"lib_footprint_issues": "warning",
|
||||||
|
"lib_footprint_mismatch": "warning",
|
||||||
|
"malformed_courtyard": "error",
|
||||||
|
"microvia_drill_out_of_range": "error",
|
||||||
|
"missing_courtyard": "ignore",
|
||||||
|
"missing_footprint": "warning",
|
||||||
|
"net_conflict": "warning",
|
||||||
|
"npth_inside_courtyard": "ignore",
|
||||||
|
"padstack": "error",
|
||||||
|
"pth_inside_courtyard": "ignore",
|
||||||
|
"shorting_items": "error",
|
||||||
|
"silk_edge_clearance": "warning",
|
||||||
|
"silk_over_copper": "error",
|
||||||
|
"silk_overlap": "error",
|
||||||
|
"skew_out_of_range": "error",
|
||||||
|
"solder_mask_bridge": "error",
|
||||||
|
"starved_thermal": "error",
|
||||||
|
"text_height": "warning",
|
||||||
|
"text_thickness": "warning",
|
||||||
|
"through_hole_pad_without_hole": "error",
|
||||||
|
"too_many_vias": "error",
|
||||||
|
"track_dangling": "warning",
|
||||||
|
"track_width": "error",
|
||||||
|
"tracks_crossing": "error",
|
||||||
|
"unconnected_items": "error",
|
||||||
|
"unresolved_variable": "error",
|
||||||
|
"via_dangling": "warning",
|
||||||
|
"zones_intersect": "error"
|
||||||
|
},
|
||||||
|
"rules": {
|
||||||
|
"allow_blind_buried_vias": false,
|
||||||
|
"allow_microvias": false,
|
||||||
|
"max_error": 0.005,
|
||||||
|
"min_clearance": 0.0,
|
||||||
|
"min_connection": 0.0,
|
||||||
|
"min_copper_edge_clearance": 0.024999999999999998,
|
||||||
|
"min_hole_clearance": 0.0,
|
||||||
|
"min_hole_to_hole": 0.25,
|
||||||
|
"min_microvia_diameter": 0.19999999999999998,
|
||||||
|
"min_microvia_drill": 0.09999999999999999,
|
||||||
|
"min_resolved_spokes": 2,
|
||||||
|
"min_silk_clearance": 0.0,
|
||||||
|
"min_text_height": 0.7,
|
||||||
|
"min_text_thickness": 0.08,
|
||||||
|
"min_through_hole_diameter": 0.19999999999999998,
|
||||||
|
"min_track_width": 0.09999999999999999,
|
||||||
|
"min_via_annular_width": 0.049999999999999996,
|
||||||
|
"min_via_diameter": 0.44999999999999996,
|
||||||
|
"solder_mask_clearance": 0.0,
|
||||||
|
"solder_mask_min_width": 0.0,
|
||||||
|
"solder_mask_to_copper_clearance": 0.0,
|
||||||
|
"use_height_for_length_calcs": true
|
||||||
|
},
|
||||||
|
"teardrop_options": [
|
||||||
|
{
|
||||||
|
"td_allow_use_two_tracks": true,
|
||||||
|
"td_curve_segcount": 5,
|
||||||
|
"td_on_pad_in_zone": false,
|
||||||
|
"td_onpadsmd": true,
|
||||||
|
"td_onroundshapesonly": false,
|
||||||
|
"td_ontrackend": false,
|
||||||
|
"td_onviapad": true
|
||||||
|
}
|
||||||
|
],
|
||||||
|
"teardrop_parameters": [
|
||||||
|
{
|
||||||
|
"td_curve_segcount": 0,
|
||||||
|
"td_height_ratio": 1.0,
|
||||||
|
"td_length_ratio": 0.5,
|
||||||
|
"td_maxheight": 2.0,
|
||||||
|
"td_maxlen": 1.0,
|
||||||
|
"td_target_name": "td_round_shape",
|
||||||
|
"td_width_to_size_filter_ratio": 0.9
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"td_curve_segcount": 0,
|
||||||
|
"td_height_ratio": 1.0,
|
||||||
|
"td_length_ratio": 0.5,
|
||||||
|
"td_maxheight": 2.0,
|
||||||
|
"td_maxlen": 1.0,
|
||||||
|
"td_target_name": "td_rect_shape",
|
||||||
|
"td_width_to_size_filter_ratio": 0.9
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"td_curve_segcount": 0,
|
||||||
|
"td_height_ratio": 1.0,
|
||||||
|
"td_length_ratio": 0.5,
|
||||||
|
"td_maxheight": 2.0,
|
||||||
|
"td_maxlen": 1.0,
|
||||||
|
"td_target_name": "td_track_end",
|
||||||
|
"td_width_to_size_filter_ratio": 0.9
|
||||||
|
}
|
||||||
|
],
|
||||||
|
"track_widths": [
|
||||||
|
0.0,
|
||||||
|
0.1,
|
||||||
|
0.11,
|
||||||
|
0.12,
|
||||||
|
0.13,
|
||||||
|
0.15,
|
||||||
|
0.2,
|
||||||
|
0.3,
|
||||||
|
0.5,
|
||||||
|
0.6,
|
||||||
|
1.0,
|
||||||
|
1.5,
|
||||||
|
2.0
|
||||||
|
],
|
||||||
|
"via_dimensions": [
|
||||||
|
{
|
||||||
|
"diameter": 0.0,
|
||||||
|
"drill": 0.0
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"diameter": 0.46,
|
||||||
|
"drill": 0.2
|
||||||
|
}
|
||||||
|
],
|
||||||
|
"zones_allow_external_fillets": false,
|
||||||
|
"zones_use_no_outline": true
|
||||||
|
},
|
||||||
|
"layer_presets": [],
|
||||||
|
"viewports": []
|
||||||
|
},
|
||||||
|
"boards": [],
|
||||||
|
"cvpcb": {
|
||||||
|
"equivalence_files": []
|
||||||
|
},
|
||||||
|
"erc": {
|
||||||
|
"erc_exclusions": [],
|
||||||
|
"meta": {
|
||||||
|
"version": 0
|
||||||
|
},
|
||||||
|
"pin_map": [
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
2,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
1,
|
||||||
|
2,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2
|
||||||
|
]
|
||||||
|
],
|
||||||
|
"rule_severities": {
|
||||||
|
"bus_definition_conflict": "error",
|
||||||
|
"bus_entry_needed": "error",
|
||||||
|
"bus_to_bus_conflict": "error",
|
||||||
|
"bus_to_net_conflict": "error",
|
||||||
|
"conflicting_netclasses": "error",
|
||||||
|
"different_unit_footprint": "error",
|
||||||
|
"different_unit_net": "error",
|
||||||
|
"duplicate_reference": "error",
|
||||||
|
"duplicate_sheet_names": "error",
|
||||||
|
"endpoint_off_grid": "warning",
|
||||||
|
"extra_units": "error",
|
||||||
|
"global_label_dangling": "warning",
|
||||||
|
"hier_label_mismatch": "error",
|
||||||
|
"label_dangling": "error",
|
||||||
|
"lib_symbol_issues": "warning",
|
||||||
|
"missing_bidi_pin": "warning",
|
||||||
|
"missing_input_pin": "warning",
|
||||||
|
"missing_power_pin": "error",
|
||||||
|
"missing_unit": "warning",
|
||||||
|
"multiple_net_names": "warning",
|
||||||
|
"net_not_bus_member": "warning",
|
||||||
|
"no_connect_connected": "warning",
|
||||||
|
"no_connect_dangling": "warning",
|
||||||
|
"pin_not_connected": "error",
|
||||||
|
"pin_not_driven": "error",
|
||||||
|
"pin_to_pin": "warning",
|
||||||
|
"power_pin_not_driven": "error",
|
||||||
|
"similar_labels": "warning",
|
||||||
|
"simulation_model_issue": "error",
|
||||||
|
"unannotated": "error",
|
||||||
|
"unit_value_mismatch": "error",
|
||||||
|
"unresolved_variable": "error",
|
||||||
|
"wire_dangling": "error"
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"libraries": {
|
||||||
|
"pinned_footprint_libs": [],
|
||||||
|
"pinned_symbol_libs": []
|
||||||
|
},
|
||||||
|
"meta": {
|
||||||
|
"filename": "pcb.kicad_pro",
|
||||||
|
"version": 1
|
||||||
|
},
|
||||||
|
"net_settings": {
|
||||||
|
"classes": [
|
||||||
|
{
|
||||||
|
"bus_width": 12,
|
||||||
|
"clearance": 0.11,
|
||||||
|
"diff_pair_gap": 0.1,
|
||||||
|
"diff_pair_via_gap": 0.25,
|
||||||
|
"diff_pair_width": 0.2,
|
||||||
|
"line_style": 0,
|
||||||
|
"microvia_diameter": 0.3,
|
||||||
|
"microvia_drill": 0.1,
|
||||||
|
"name": "Default",
|
||||||
|
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"track_width": 0.11,
|
||||||
|
"via_diameter": 0.45,
|
||||||
|
"via_drill": 0.2,
|
||||||
|
"wire_width": 6
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"bus_width": 12,
|
||||||
|
"clearance": 0.11,
|
||||||
|
"diff_pair_gap": 0.11,
|
||||||
|
"diff_pair_via_gap": 0.25,
|
||||||
|
"diff_pair_width": 0.15,
|
||||||
|
"line_style": 0,
|
||||||
|
"microvia_diameter": 0.3,
|
||||||
|
"microvia_drill": 0.1,
|
||||||
|
"name": "DP",
|
||||||
|
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"track_width": 0.15,
|
||||||
|
"via_diameter": 0.45,
|
||||||
|
"via_drill": 0.2,
|
||||||
|
"wire_width": 6
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"bus_width": 12,
|
||||||
|
"clearance": 0.11,
|
||||||
|
"diff_pair_gap": 0.25,
|
||||||
|
"diff_pair_via_gap": 0.25,
|
||||||
|
"diff_pair_width": 0.2,
|
||||||
|
"line_style": 0,
|
||||||
|
"microvia_diameter": 0.3,
|
||||||
|
"microvia_drill": 0.1,
|
||||||
|
"name": "EPD",
|
||||||
|
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"track_width": 0.11,
|
||||||
|
"via_diameter": 0.45,
|
||||||
|
"via_drill": 0.2,
|
||||||
|
"wire_width": 6
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"bus_width": 12,
|
||||||
|
"clearance": 0.11,
|
||||||
|
"diff_pair_gap": 0.11,
|
||||||
|
"diff_pair_via_gap": 0.25,
|
||||||
|
"diff_pair_width": 0.15,
|
||||||
|
"line_style": 0,
|
||||||
|
"microvia_diameter": 0.3,
|
||||||
|
"microvia_drill": 0.1,
|
||||||
|
"name": "LVDS",
|
||||||
|
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"track_width": 0.15,
|
||||||
|
"via_diameter": 0.45,
|
||||||
|
"via_drill": 0.2,
|
||||||
|
"wire_width": 6
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"bus_width": 12,
|
||||||
|
"clearance": 0.1,
|
||||||
|
"diff_pair_gap": 0.1,
|
||||||
|
"diff_pair_via_gap": 0.25,
|
||||||
|
"diff_pair_width": 0.1,
|
||||||
|
"line_style": 0,
|
||||||
|
"microvia_diameter": 0.3,
|
||||||
|
"microvia_drill": 0.1,
|
||||||
|
"name": "SDRAM_A",
|
||||||
|
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"track_width": 0.1,
|
||||||
|
"via_diameter": 0.45,
|
||||||
|
"via_drill": 0.2,
|
||||||
|
"wire_width": 6
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"bus_width": 12,
|
||||||
|
"clearance": 0.1,
|
||||||
|
"diff_pair_gap": 0.1,
|
||||||
|
"diff_pair_via_gap": 0.25,
|
||||||
|
"diff_pair_width": 0.1,
|
||||||
|
"line_style": 0,
|
||||||
|
"microvia_diameter": 0.3,
|
||||||
|
"microvia_drill": 0.1,
|
||||||
|
"name": "SDRAM_H",
|
||||||
|
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"track_width": 0.1,
|
||||||
|
"via_diameter": 0.45,
|
||||||
|
"via_drill": 0.2,
|
||||||
|
"wire_width": 6
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"bus_width": 12,
|
||||||
|
"clearance": 0.1,
|
||||||
|
"diff_pair_gap": 0.1,
|
||||||
|
"diff_pair_via_gap": 0.25,
|
||||||
|
"diff_pair_width": 0.1,
|
||||||
|
"line_style": 0,
|
||||||
|
"microvia_diameter": 0.3,
|
||||||
|
"microvia_drill": 0.1,
|
||||||
|
"name": "SDRAM_L",
|
||||||
|
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"track_width": 0.1,
|
||||||
|
"via_diameter": 0.45,
|
||||||
|
"via_drill": 0.2,
|
||||||
|
"wire_width": 6
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"bus_width": 12,
|
||||||
|
"clearance": 0.11,
|
||||||
|
"diff_pair_gap": 0.11,
|
||||||
|
"diff_pair_via_gap": 0.25,
|
||||||
|
"diff_pair_width": 0.18,
|
||||||
|
"line_style": 0,
|
||||||
|
"microvia_diameter": 0.3,
|
||||||
|
"microvia_drill": 0.1,
|
||||||
|
"name": "USB",
|
||||||
|
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"track_width": 0.15,
|
||||||
|
"via_diameter": 0.45,
|
||||||
|
"via_drill": 0.2,
|
||||||
|
"wire_width": 6
|
||||||
|
}
|
||||||
|
],
|
||||||
|
"meta": {
|
||||||
|
"version": 3
|
||||||
|
},
|
||||||
|
"net_colors": {
|
||||||
|
"+1V1": "rgb(255, 92, 56)",
|
||||||
|
"+1V35": "rgb(185, 61, 143)",
|
||||||
|
"+3V3": "rgb(179, 228, 50)",
|
||||||
|
"+5V": "rgb(255, 122, 107)",
|
||||||
|
"GND": "rgb(0, 94, 255)"
|
||||||
|
},
|
||||||
|
"netclass_assignments": null,
|
||||||
|
"netclass_patterns": [
|
||||||
|
{
|
||||||
|
"netclass": "EPD",
|
||||||
|
"pattern": "/eink/ED*"
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"netclass": "EPD",
|
||||||
|
"pattern": "EPDC_*"
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"netclass": "SDRAM_A",
|
||||||
|
"pattern": "/fpga_ddr/DRAM_*"
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"netclass": "EPD",
|
||||||
|
"pattern": "/eink/ES*"
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"netclass": "LVDS",
|
||||||
|
"pattern": "TMDS*"
|
||||||
|
}
|
||||||
|
]
|
||||||
|
},
|
||||||
|
"pcbnew": {
|
||||||
|
"last_paths": {
|
||||||
|
"gencad": "",
|
||||||
|
"idf": "",
|
||||||
|
"netlist": "",
|
||||||
|
"specctra_dsn": "",
|
||||||
|
"step": "",
|
||||||
|
"vrml": ""
|
||||||
|
},
|
||||||
|
"page_layout_descr_file": ""
|
||||||
|
},
|
||||||
|
"schematic": {
|
||||||
|
"annotate_start_num": 400,
|
||||||
|
"drawing": {
|
||||||
|
"dashed_lines_dash_length_ratio": 12.0,
|
||||||
|
"dashed_lines_gap_length_ratio": 3.0,
|
||||||
|
"default_bus_thickness": 12.0,
|
||||||
|
"default_line_thickness": 6.0,
|
||||||
|
"default_text_size": 50.0,
|
||||||
|
"default_wire_thickness": 6.0,
|
||||||
|
"field_names": [],
|
||||||
|
"intersheets_ref_own_page": false,
|
||||||
|
"intersheets_ref_prefix": "",
|
||||||
|
"intersheets_ref_short": false,
|
||||||
|
"intersheets_ref_show": false,
|
||||||
|
"intersheets_ref_suffix": "",
|
||||||
|
"junction_size_choice": 3,
|
||||||
|
"label_size_ratio": 0.375,
|
||||||
|
"pin_symbol_size": 25.0,
|
||||||
|
"text_offset_ratio": 0.15
|
||||||
|
},
|
||||||
|
"legacy_lib_dir": "",
|
||||||
|
"legacy_lib_list": [],
|
||||||
|
"meta": {
|
||||||
|
"version": 1
|
||||||
|
},
|
||||||
|
"net_format_name": "",
|
||||||
|
"ngspice": {
|
||||||
|
"fix_include_paths": true,
|
||||||
|
"fix_passive_vals": false,
|
||||||
|
"meta": {
|
||||||
|
"version": 0
|
||||||
|
},
|
||||||
|
"model_mode": 0,
|
||||||
|
"workbook_filename": ""
|
||||||
|
},
|
||||||
|
"page_layout_descr_file": "",
|
||||||
|
"plot_directory": "./",
|
||||||
|
"spice_adjust_passive_values": false,
|
||||||
|
"spice_current_sheet_as_root": false,
|
||||||
|
"spice_external_command": "spice \"%I\"",
|
||||||
|
"spice_model_current_sheet_as_root": true,
|
||||||
|
"spice_save_all_currents": false,
|
||||||
|
"spice_save_all_voltages": false,
|
||||||
|
"subpart_first_id": 65,
|
||||||
|
"subpart_id_separator": 0
|
||||||
|
},
|
||||||
|
"sheets": [
|
||||||
|
[
|
||||||
|
"4654897e-3e2f-4522-96c3-20b19803c088",
|
||||||
|
""
|
||||||
|
],
|
||||||
|
[
|
||||||
|
"0606a719-6980-4867-837f-aa642737d361",
|
||||||
|
"power"
|
||||||
|
],
|
||||||
|
[
|
||||||
|
"35d2a4e1-1cb2-4b6c-a7fb-e3a9449d4ff3",
|
||||||
|
"fpga"
|
||||||
|
],
|
||||||
|
[
|
||||||
|
"b1d5941d-0481-47a2-a434-0b8e587a166a",
|
||||||
|
"eink"
|
||||||
|
],
|
||||||
|
[
|
||||||
|
"866a5b4a-453a-413a-94a2-5e610f40d8dd",
|
||||||
|
"fpga_ddr"
|
||||||
|
],
|
||||||
|
[
|
||||||
|
"80373716-d41f-4f06-92dd-577434075703",
|
||||||
|
"dp_in"
|
||||||
|
]
|
||||||
|
],
|
||||||
|
"text_variables": {}
|
||||||
|
}
|
127
pcb/mainboard_lite/pcb.kicad_sch
Normal file
127
pcb/mainboard_lite/pcb.kicad_sch
Normal file
|
@ -0,0 +1,127 @@
|
||||||
|
(kicad_sch (version 20230121) (generator eeschema)
|
||||||
|
|
||||||
|
(uuid 4654897e-3e2f-4522-96c3-20b19803c088)
|
||||||
|
|
||||||
|
(paper "A4")
|
||||||
|
|
||||||
|
(title_block
|
||||||
|
(title "Glider Lite")
|
||||||
|
(date "2023-12-24")
|
||||||
|
(rev "R0.7")
|
||||||
|
(company "Copyright 2023 Modos / Engineer: Wenting Zhang")
|
||||||
|
)
|
||||||
|
|
||||||
|
(lib_symbols
|
||||||
|
)
|
||||||
|
|
||||||
|
|
||||||
|
(text "FPGA DDR Memory" (at 35.56 67.31 0)
|
||||||
|
(effects (font (size 2.54 2.54)) (justify left bottom))
|
||||||
|
(uuid 36b30dff-23e2-4ed9-971b-1df779950e92)
|
||||||
|
)
|
||||||
|
(text "Power Supply" (at 35.56 33.02 0)
|
||||||
|
(effects (font (size 2.54 2.54)) (justify left bottom))
|
||||||
|
(uuid 558a13be-3757-4ba7-9c3e-24eef7c78d0f)
|
||||||
|
)
|
||||||
|
(text "Display" (at 35.56 55.88 0)
|
||||||
|
(effects (font (size 2.54 2.54)) (justify left bottom))
|
||||||
|
(uuid d2b3e5ed-56f7-4162-ab02-9bde306dbf5a)
|
||||||
|
)
|
||||||
|
(text "FPGA Core" (at 35.56 44.45 0)
|
||||||
|
(effects (font (size 2.54 2.54)) (justify left bottom))
|
||||||
|
(uuid edafe42e-7b4b-443d-9c19-73868867df97)
|
||||||
|
)
|
||||||
|
(text "TMDS Input" (at 35.56 78.74 0)
|
||||||
|
(effects (font (size 2.54 2.54)) (justify left bottom))
|
||||||
|
(uuid fbc25d2d-afe2-4ffb-9abb-3b9e35c79f93)
|
||||||
|
)
|
||||||
|
|
||||||
|
(sheet (at 33.02 27.94) (size 53.34 6.35) (fields_autoplaced)
|
||||||
|
(stroke (width 0.1524) (type solid))
|
||||||
|
(fill (color 0 0 0 0.0000))
|
||||||
|
(uuid 0606a719-6980-4867-837f-aa642737d361)
|
||||||
|
(property "Sheetname" "power" (at 33.02 27.2284 0)
|
||||||
|
(effects (font (size 1.27 1.27)) (justify left bottom))
|
||||||
|
)
|
||||||
|
(property "Sheetfile" "power.kicad_sch" (at 33.02 34.8746 0)
|
||||||
|
(effects (font (size 1.27 1.27)) (justify left top))
|
||||||
|
)
|
||||||
|
(instances
|
||||||
|
(project "pcb"
|
||||||
|
(path "/4654897e-3e2f-4522-96c3-20b19803c088" (page "1"))
|
||||||
|
)
|
||||||
|
)
|
||||||
|
)
|
||||||
|
|
||||||
|
(sheet (at 33.02 39.37) (size 53.34 6.35) (fields_autoplaced)
|
||||||
|
(stroke (width 0.1524) (type solid))
|
||||||
|
(fill (color 0 0 0 0.0000))
|
||||||
|
(uuid 35d2a4e1-1cb2-4b6c-a7fb-e3a9449d4ff3)
|
||||||
|
(property "Sheetname" "fpga" (at 33.02 38.6584 0)
|
||||||
|
(effects (font (size 1.27 1.27)) (justify left bottom))
|
||||||
|
)
|
||||||
|
(property "Sheetfile" "fpga.kicad_sch" (at 33.02 46.3046 0)
|
||||||
|
(effects (font (size 1.27 1.27)) (justify left top))
|
||||||
|
)
|
||||||
|
(instances
|
||||||
|
(project "pcb"
|
||||||
|
(path "/4654897e-3e2f-4522-96c3-20b19803c088" (page "2"))
|
||||||
|
)
|
||||||
|
)
|
||||||
|
)
|
||||||
|
|
||||||
|
(sheet (at 33.02 73.66) (size 53.34 6.35) (fields_autoplaced)
|
||||||
|
(stroke (width 0.1524) (type solid))
|
||||||
|
(fill (color 0 0 0 0.0000))
|
||||||
|
(uuid 80373716-d41f-4f06-92dd-577434075703)
|
||||||
|
(property "Sheetname" "dp_in" (at 33.02 72.9484 0)
|
||||||
|
(effects (font (size 1.27 1.27)) (justify left bottom))
|
||||||
|
)
|
||||||
|
(property "Sheetfile" "dp_in.kicad_sch" (at 33.02 80.5946 0)
|
||||||
|
(effects (font (size 1.27 1.27)) (justify left top))
|
||||||
|
)
|
||||||
|
(instances
|
||||||
|
(project "pcb"
|
||||||
|
(path "/4654897e-3e2f-4522-96c3-20b19803c088" (page "7"))
|
||||||
|
)
|
||||||
|
)
|
||||||
|
)
|
||||||
|
|
||||||
|
(sheet (at 33.02 62.23) (size 53.34 6.35) (fields_autoplaced)
|
||||||
|
(stroke (width 0.1524) (type solid))
|
||||||
|
(fill (color 0 0 0 0.0000))
|
||||||
|
(uuid 866a5b4a-453a-413a-94a2-5e610f40d8dd)
|
||||||
|
(property "Sheetname" "fpga_ddr" (at 33.02 61.5184 0)
|
||||||
|
(effects (font (size 1.27 1.27)) (justify left bottom))
|
||||||
|
)
|
||||||
|
(property "Sheetfile" "fpga_ddr.kicad_sch" (at 33.02 69.1646 0)
|
||||||
|
(effects (font (size 1.27 1.27)) (justify left top))
|
||||||
|
)
|
||||||
|
(instances
|
||||||
|
(project "pcb"
|
||||||
|
(path "/4654897e-3e2f-4522-96c3-20b19803c088" (page "5"))
|
||||||
|
)
|
||||||
|
)
|
||||||
|
)
|
||||||
|
|
||||||
|
(sheet (at 33.02 50.8) (size 53.34 6.35) (fields_autoplaced)
|
||||||
|
(stroke (width 0.1524) (type solid))
|
||||||
|
(fill (color 0 0 0 0.0000))
|
||||||
|
(uuid b1d5941d-0481-47a2-a434-0b8e587a166a)
|
||||||
|
(property "Sheetname" "eink" (at 33.02 50.0884 0)
|
||||||
|
(effects (font (size 1.27 1.27)) (justify left bottom))
|
||||||
|
)
|
||||||
|
(property "Sheetfile" "eink.kicad_sch" (at 33.02 57.7346 0)
|
||||||
|
(effects (font (size 1.27 1.27)) (justify left top))
|
||||||
|
)
|
||||||
|
(instances
|
||||||
|
(project "pcb"
|
||||||
|
(path "/4654897e-3e2f-4522-96c3-20b19803c088" (page "3"))
|
||||||
|
)
|
||||||
|
)
|
||||||
|
)
|
||||||
|
|
||||||
|
(sheet_instances
|
||||||
|
(path "/" (page "0"))
|
||||||
|
)
|
||||||
|
)
|
5656
pcb/mainboard_lite/power.kicad_sch
Normal file
5656
pcb/mainboard_lite/power.kicad_sch
Normal file
File diff suppressed because it is too large
Load diff
4
pcb/mainboard_lite/sym-lib-table
Executable file
4
pcb/mainboard_lite/sym-lib-table
Executable file
|
@ -0,0 +1,4 @@
|
||||||
|
(sym_lib_table
|
||||||
|
(version 7)
|
||||||
|
(lib (name "symbols")(type "KiCad")(uri "${KIPRJMOD}/../common/symbols.kicad_sym")(options "")(descr ""))
|
||||||
|
)
|
Loading…
Reference in a new issue