r0p7 layout done

This commit is contained in:
Wenting Zhang 2024-02-12 00:27:17 -05:00
parent 19e07df396
commit 8ccf2bdbff
14 changed files with 155851 additions and 21155 deletions

View file

@ -32,3 +32,4 @@ Lite R0.1
R0.7
1. Import DVI TMDS input, newly revised power supply and user button from RL0.1
2. Connect FPGA to RP2040's hardware SPI
3. Fix USB Type C mux connection

View file

@ -1,429 +1,511 @@
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View file

@ -0,0 +1,466 @@
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"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.127,
"via_diameter": 0.45,
@ -595,14 +616,14 @@
"clearance": 0.11,
"diff_pair_gap": 0.11,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.18,
"diff_pair_width": 0.15,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "USB",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.15,
"track_width": 0.11,
"via_diameter": 0.45,
"via_drill": 0.3,
"wire_width": 6
@ -613,9 +634,11 @@
},
"net_colors": {
"+1V0": "rgb(255, 92, 56)",
"+1V2": "rgb(255, 117, 0)",
"+1V35": "rgb(185, 61, 143)",
"+3V3": "rgb(179, 228, 50)",
"+5V": "rgb(255, 122, 107)",
"+5V_EPD": "rgb(255, 37, 28)",
"GND": "rgb(0, 94, 255)"
},
"netclass_assignments": null,
@ -638,7 +661,7 @@
},
{
"netclass": "LVDS",
"pattern": "TMDS*"
"pattern": "LVDS*"
},
{
"netclass": "SDRAM_L",
@ -659,6 +682,30 @@
{
"netclass": "SDRAM_H",
"pattern": "/fpga_ddr/DRAM_U*"
},
{
"netclass": "DP",
"pattern": "/dp_in/*"
},
{
"netclass": "LVDS",
"pattern": "*TMDS*"
},
{
"netclass": "POWER",
"pattern": "+*"
},
{
"netclass": "POWER",
"pattern": "GND"
},
{
"netclass": "POWER",
"pattern": "V*"
},
{
"netclass": "USB",
"pattern": "USB*"
}
]
},
@ -667,7 +714,7 @@
"gencad": "",
"idf": "",
"netlist": "",
"plot": "",
"plot": "gerber/",
"pos_files": "",
"specctra_dsn": "",
"step": "pcb.step",

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