From 1120e9958d3ebbdad209284a07b2792ae2dc4eef Mon Sep 17 00:00:00 2001
From: Wenting Zhang <zephray@outlook.com>
Date: Mon, 19 May 2025 12:32:25 +0800
Subject: [PATCH] Enable power monitoring

---
 .gitignore                                    |    2 +
 fw/.cproject                                  |    4 +-
 fw/.mxproject                                 |    2 +-
 fw/Core/Inc/main.h                            |    2 -
 fw/Core/Inc/stm32h7xx_it.h                    |    1 +
 fw/Core/Src/main.c                            |  154 +-
 fw/Core/Src/stm32h7xx_hal_msp.c               |   99 +-
 fw/Core/Src/stm32h7xx_it.c                    |   15 +
 .../Inc/stm32h7xx_ll_tim.h                    | 5213 -----------------
 fw/User/adv7611.c                             |   26 +-
 fw/User/adv7611.h                             |    1 +
 fw/User/app_main.c                            |    4 +-
 fw/User/board.h                               |    1 +
 fw/User/config.c                              |  126 +-
 fw/User/config.h                              |    1 +
 fw/User/fpga.c                                |   14 +-
 fw/User/fpga.h                                |    5 +-
 fw/User/power.c                               |  129 +-
 fw/User/power.h                               |   22 +
 fw/User/ptn3460.c                             |    4 +
 fw/User/shell/shell.c                         |   28 +-
 fw/User/shell/shell_cmds.c                    |  567 +-
 fw/User/usbapp.c                              |    4 +-
 fw/glider_ec_rtos.ioc                         |  147 +-
 24 files changed, 817 insertions(+), 5754 deletions(-)
 delete mode 100644 fw/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_tim.h

diff --git a/.gitignore b/.gitignore
index fd28f4a..98588e6 100644
--- a/.gitignore
+++ b/.gitignore
@@ -10,3 +10,5 @@ production/
 fp-info-cache
 fabrication-toolkit-options.json
 *.kicad_sch-bak
+# MCUXpresso files
+Debug/
diff --git a/fw/.cproject b/fw/.cproject
index 98453b8..297e616 100644
--- a/fw/.cproject
+++ b/fw/.cproject
@@ -26,11 +26,11 @@
 							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.661195920" name="Defaults" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" useByScannerDiscovery="false" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.6 || Debug || true || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.option.toolchain.value.workspace || STM32H750VBTx || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../Core/Inc | ../Drivers/STM32H7xx_HAL_Driver/Inc | ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy | ../Drivers/CMSIS/Device/ST/STM32H7xx/Include | ../Drivers/CMSIS/Include | ../Middlewares/ST/filex/common/inc/ | ../Middlewares/ST/filex/ports/generic/inc/ | ../Middlewares/ST/usbx/common/core/inc/ | ../Middlewares/ST/usbx/ports/generic/inc/ | ../Middlewares/ST/usbx/common/usbx_stm32_device_controllers/ | ../Middlewares/ST/usbx/common/usbx_device_classes/inc/ | ../Middlewares/ST/levelx/common/inc/ | ../Middlewares/ST/threadx/common/inc/ | ../Middlewares/ST/threadx/ports/cortex_m7/gnu/inc/ | ../Middlewares/ST/threadx/utility/low_power/ | ../Middlewares/Third_Party/FreeRTOS/Source/include | ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 | ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F ||  ||  || USE_PWR_LDO_SUPPLY | USE_HAL_DRIVER | STM32H750xx | USE_FULL_LL_DRIVER ||  || Drivers | Core/Startup | Middlewares | Core ||  ||  || ${workspace_loc:/${ProjName}/STM32H750VBTX_FLASH.ld} || true || NonSecure ||  || secure_nsclib.o ||  || None ||  ||  || " valueType="string"/>
 							<option id="com.st.stm32cube.ide.mcu.debug.option.cpuclock.1193428585" name="Cpu clock frequence" superClass="com.st.stm32cube.ide.mcu.debug.option.cpuclock" useByScannerDiscovery="false" value="48" valueType="string"/>
 							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.nanoprintffloat.213716470" name="Use float with printf from newlib-nano (-u _printf_float)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.nanoprintffloat" useByScannerDiscovery="false" value="true" valueType="boolean"/>
-							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.convertbinary.1776475681" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.convertbinary" value="true" valueType="boolean"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.convertbinary.1776475681" name="Convert to binary file (-O binary)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.convertbinary" useByScannerDiscovery="false" value="true" valueType="boolean"/>
 							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform.851652527" isAbstract="false" osList="all" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform"/>
 							<builder buildPath="${workspace_loc:/glider_ec_rtos}/Debug" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder.1203074036" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder"/>
 							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.1274958836" name="MCU/MPU GCC Assembler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler">
-								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.1793326124" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.value.g3" valueType="enumerated"/>
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.1793326124" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.value.g1" valueType="enumerated"/>
 								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.definedsymbols.1840179548" name="Define symbols (-D)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.definedsymbols" valueType="definedSymbols">
 									<listOptionValue builtIn="false" value="DEBUG"/>
 								</option>
diff --git a/fw/.mxproject b/fw/.mxproject
index c1f478d..689600b 100644
--- a/fw/.mxproject
+++ b/fw/.mxproject
@@ -1,5 +1,5 @@
 [PreviousLibFiles]
-LibFiles=Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_tim.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_tim_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_adc.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_adc_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_adc.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_rcc.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_rcc_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_bus.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_rcc.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_crs.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_system.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_utils.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_flash.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_flash_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_gpio.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_gpio_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_gpio.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_hsem.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_hsem.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_dma.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_dma_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_dma.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_dmamux.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_mdma.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_pwr.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_pwr_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_pwr.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_cortex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_cortex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_def.h;Drivers\STM32H7xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_i2c.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_i2c_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_exti.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_exti.h;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_exti.c;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_dac.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_dac.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_dac_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_fmc.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_nor.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_sram.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_nand.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_sdram.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_i2c.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_qspi.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_delayblock.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_sdmmc.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_sd.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_sd_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_mmc.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_mmc_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_spi.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_spi.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_spi_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_tim.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_pcd.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_pcd_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_usb.h;Middlewares\Third_Party\FreeRTOS\Source\include\croutine.h;Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h;Middlewares\Third_Party\FreeRTOS\Source\include\event_groups.h;Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h;Middlewares\Third_Party\FreeRTOS\Source\include\list.h;Middlewares\Third_Party\FreeRTOS\Source\include\message_buffer.h;Middlewares\Third_Party\FreeRTOS\Source\include\mpu_prototypes.h;Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h;Middlewares\Third_Party\FreeRTOS\Source\include\portable.h;Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h;Middlewares\Third_Party\FreeRTOS\Source\include\queue.h;Middlewares\Third_Party\FreeRTOS\Source\include\semphr.h;Middlewares\Third_Party\FreeRTOS\Source\include\stack_macros.h;Middlewares\Third_Party\FreeRTOS\Source\include\StackMacros.h;Middlewares\Third_Party\FreeRTOS\Source\include\stream_buffer.h;Middlewares\Third_Party\FreeRTOS\Source\include\task.h;Middlewares\Third_Party\FreeRTOS\Source\include\timers.h;Middlewares\Third_Party\FreeRTOS\Source\include\atomic.h;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os.h;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\freertos_mpool.h;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\freertos_os2.h;Middlewares\Third_Party\FreeRTOS\Source\portable\GCC\ARM_CM4F\portmacro.h;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_tim.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_tim_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_adc.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_adc_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_flash.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_flash_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_gpio.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_hsem.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_mdma.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cortex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2c.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2c_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_exti.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_rcc.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_utils.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dac.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dac_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_fmc.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_nor.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_sram.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_nand.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_sdram.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_i2c.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_gpio.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_exti.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_dma.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_qspi.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_delayblock.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_sdmmc.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_sd.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_sd_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_mmc.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_mmc_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_spi.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_spi_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pcd.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pcd_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_usb.c;Middlewares\Third_Party\FreeRTOS\Source\croutine.c;Middlewares\Third_Party\FreeRTOS\Source\event_groups.c;Middlewares\Third_Party\FreeRTOS\Source\list.c;Middlewares\Third_Party\FreeRTOS\Source\queue.c;Middlewares\Third_Party\FreeRTOS\Source\stream_buffer.c;Middlewares\Third_Party\FreeRTOS\Source\tasks.c;Middlewares\Third_Party\FreeRTOS\Source\timers.c;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.c;Middlewares\Third_Party\FreeRTOS\Source\portable\MemMang\heap_4.c;Middlewares\Third_Party\FreeRTOS\Source\portable\GCC\ARM_CM4F\port.c;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_tim.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_tim_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_adc.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_adc_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_adc.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_rcc.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_rcc_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_bus.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_rcc.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_crs.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_system.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_utils.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_flash.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_flash_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_gpio.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_gpio_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_gpio.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_hsem.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_hsem.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_dma.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_dma_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_dma.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_dmamux.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_mdma.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_pwr.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_pwr_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_pwr.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_cortex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_cortex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_def.h;Drivers\STM32H7xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_i2c.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_i2c_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_exti.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_exti.h;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_exti.c;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_dac.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_dac.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_dac_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_fmc.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_nor.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_sram.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_nand.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_sdram.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_i2c.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_qspi.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_delayblock.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_sdmmc.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_sd.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_sd_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_mmc.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_mmc_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_spi.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_spi.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_spi_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_tim.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_pcd.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_pcd_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_usb.h;Middlewares\Third_Party\FreeRTOS\Source\include\croutine.h;Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h;Middlewares\Third_Party\FreeRTOS\Source\include\event_groups.h;Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h;Middlewares\Third_Party\FreeRTOS\Source\include\list.h;Middlewares\Third_Party\FreeRTOS\Source\include\message_buffer.h;Middlewares\Third_Party\FreeRTOS\Source\include\mpu_prototypes.h;Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h;Middlewares\Third_Party\FreeRTOS\Source\include\portable.h;Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h;Middlewares\Third_Party\FreeRTOS\Source\include\queue.h;Middlewares\Third_Party\FreeRTOS\Source\include\semphr.h;Middlewares\Third_Party\FreeRTOS\Source\include\stack_macros.h;Middlewares\Third_Party\FreeRTOS\Source\include\StackMacros.h;Middlewares\Third_Party\FreeRTOS\Source\include\stream_buffer.h;Middlewares\Third_Party\FreeRTOS\Source\include\task.h;Middlewares\Third_Party\FreeRTOS\Source\include\timers.h;Middlewares\Third_Party\FreeRTOS\Source\include\atomic.h;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os.h;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\freertos_mpool.h;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\freertos_os2.h;Middlewares\Third_Party\FreeRTOS\Source\portable\GCC\ARM_CM4F\portmacro.h;Drivers\CMSIS\Device\ST\STM32H7xx\Include\stm32h750xx.h;Drivers\CMSIS\Device\ST\STM32H7xx\Include\stm32h7xx.h;Drivers\CMSIS\Device\ST\STM32H7xx\Include\system_stm32h7xx.h;Drivers\CMSIS\Device\ST\STM32H7xx\Include\system_stm32h7xx.h;Drivers\CMSIS\Device\ST\STM32H7xx\Source\Templates\system_stm32h7xx.c;Drivers\CMSIS\Include\cmsis_armcc.h;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_armclang_ltm.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_armv81mml.h;Drivers\CMSIS\Include\core_armv8mbl.h;Drivers\CMSIS\Include\core_armv8mml.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm35p.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\mpu_armv7.h;Drivers\CMSIS\Include\mpu_armv8.h;Drivers\CMSIS\Include\tz_context.h;
+LibFiles=Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_tim.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_tim_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_adc.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_adc_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_adc.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_rcc.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_rcc_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_bus.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_rcc.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_crs.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_system.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_utils.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_flash.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_flash_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_gpio.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_gpio_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_gpio.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_hsem.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_hsem.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_dma.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_dma_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_dma.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_dmamux.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_mdma.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_pwr.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_pwr_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_pwr.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_cortex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_cortex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_def.h;Drivers\STM32H7xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_i2c.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_i2c_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_exti.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_exti.h;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_exti.c;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_dac.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_dac.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_dac_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_fmc.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_nor.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_sram.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_nand.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_sdram.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_i2c.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_qspi.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_delayblock.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_sdmmc.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_sd.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_sd_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_mmc.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_mmc_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_spi.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_spi.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_spi_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_pcd.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_pcd_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_usb.h;Middlewares\Third_Party\FreeRTOS\Source\include\croutine.h;Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h;Middlewares\Third_Party\FreeRTOS\Source\include\event_groups.h;Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h;Middlewares\Third_Party\FreeRTOS\Source\include\list.h;Middlewares\Third_Party\FreeRTOS\Source\include\message_buffer.h;Middlewares\Third_Party\FreeRTOS\Source\include\mpu_prototypes.h;Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h;Middlewares\Third_Party\FreeRTOS\Source\include\portable.h;Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h;Middlewares\Third_Party\FreeRTOS\Source\include\queue.h;Middlewares\Third_Party\FreeRTOS\Source\include\semphr.h;Middlewares\Third_Party\FreeRTOS\Source\include\stack_macros.h;Middlewares\Third_Party\FreeRTOS\Source\include\StackMacros.h;Middlewares\Third_Party\FreeRTOS\Source\include\stream_buffer.h;Middlewares\Third_Party\FreeRTOS\Source\include\task.h;Middlewares\Third_Party\FreeRTOS\Source\include\timers.h;Middlewares\Third_Party\FreeRTOS\Source\include\atomic.h;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os.h;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\freertos_mpool.h;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\freertos_os2.h;Middlewares\Third_Party\FreeRTOS\Source\portable\GCC\ARM_CM4F\portmacro.h;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_tim.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_tim_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_adc.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_adc_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_flash.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_flash_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_gpio.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_hsem.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_mdma.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cortex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2c.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2c_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_exti.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_rcc.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_utils.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dac.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dac_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_fmc.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_nor.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_sram.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_nand.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_sdram.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_i2c.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_gpio.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_exti.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_dma.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_qspi.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_delayblock.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_sdmmc.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_sd.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_sd_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_mmc.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_mmc_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_spi.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_spi_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pcd.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pcd_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_usb.c;Middlewares\Third_Party\FreeRTOS\Source\croutine.c;Middlewares\Third_Party\FreeRTOS\Source\event_groups.c;Middlewares\Third_Party\FreeRTOS\Source\list.c;Middlewares\Third_Party\FreeRTOS\Source\queue.c;Middlewares\Third_Party\FreeRTOS\Source\stream_buffer.c;Middlewares\Third_Party\FreeRTOS\Source\tasks.c;Middlewares\Third_Party\FreeRTOS\Source\timers.c;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.c;Middlewares\Third_Party\FreeRTOS\Source\portable\MemMang\heap_4.c;Middlewares\Third_Party\FreeRTOS\Source\portable\GCC\ARM_CM4F\port.c;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_tim.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_tim_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_adc.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_adc_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_adc.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_rcc.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_rcc_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_bus.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_rcc.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_crs.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_system.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_utils.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_flash.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_flash_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_gpio.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_gpio_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_gpio.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_hsem.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_hsem.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_dma.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_dma_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_dma.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_dmamux.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_mdma.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_pwr.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_pwr_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_pwr.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_cortex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_cortex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_def.h;Drivers\STM32H7xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_i2c.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_i2c_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_exti.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_exti.h;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_exti.c;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_dac.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_dac.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_dac_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_fmc.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_nor.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_sram.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_nand.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_sdram.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_i2c.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_qspi.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_delayblock.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_sdmmc.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_sd.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_sd_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_mmc.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_mmc_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_spi.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_spi.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_spi_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_pcd.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_pcd_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_usb.h;Middlewares\Third_Party\FreeRTOS\Source\include\croutine.h;Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h;Middlewares\Third_Party\FreeRTOS\Source\include\event_groups.h;Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h;Middlewares\Third_Party\FreeRTOS\Source\include\list.h;Middlewares\Third_Party\FreeRTOS\Source\include\message_buffer.h;Middlewares\Third_Party\FreeRTOS\Source\include\mpu_prototypes.h;Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h;Middlewares\Third_Party\FreeRTOS\Source\include\portable.h;Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h;Middlewares\Third_Party\FreeRTOS\Source\include\queue.h;Middlewares\Third_Party\FreeRTOS\Source\include\semphr.h;Middlewares\Third_Party\FreeRTOS\Source\include\stack_macros.h;Middlewares\Third_Party\FreeRTOS\Source\include\StackMacros.h;Middlewares\Third_Party\FreeRTOS\Source\include\stream_buffer.h;Middlewares\Third_Party\FreeRTOS\Source\include\task.h;Middlewares\Third_Party\FreeRTOS\Source\include\timers.h;Middlewares\Third_Party\FreeRTOS\Source\include\atomic.h;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os.h;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\freertos_mpool.h;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\freertos_os2.h;Middlewares\Third_Party\FreeRTOS\Source\portable\GCC\ARM_CM4F\portmacro.h;Drivers\CMSIS\Device\ST\STM32H7xx\Include\stm32h750xx.h;Drivers\CMSIS\Device\ST\STM32H7xx\Include\stm32h7xx.h;Drivers\CMSIS\Device\ST\STM32H7xx\Include\system_stm32h7xx.h;Drivers\CMSIS\Device\ST\STM32H7xx\Include\system_stm32h7xx.h;Drivers\CMSIS\Device\ST\STM32H7xx\Source\Templates\system_stm32h7xx.c;Drivers\CMSIS\Include\cmsis_armcc.h;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_armclang_ltm.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_armv81mml.h;Drivers\CMSIS\Include\core_armv8mbl.h;Drivers\CMSIS\Include\core_armv8mml.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm35p.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\mpu_armv7.h;Drivers\CMSIS\Include\mpu_armv8.h;Drivers\CMSIS\Include\tz_context.h;
 
 [PreviousUsedCubeIDEFiles]
 SourceFiles=Core\Src\main.c;Core\Src\freertos.c;Core\Src\stm32h7xx_it.c;Core\Src\stm32h7xx_hal_msp.c;Core\Src\stm32h7xx_hal_timebase_tim.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_exti.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_tim.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_tim_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_adc.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_adc_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_flash.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_flash_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_gpio.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_hsem.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_mdma.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cortex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2c.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2c_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_exti.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_rcc.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_utils.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dac.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dac_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_fmc.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_nor.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_sram.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_nand.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_sdram.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_i2c.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_gpio.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_dma.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_qspi.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_delayblock.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_sdmmc.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_sd.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_sd_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_mmc.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_mmc_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_spi.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_spi_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pcd.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pcd_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_usb.c;Middlewares\Third_Party\FreeRTOS\Source\croutine.c;Middlewares\Third_Party\FreeRTOS\Source\event_groups.c;Middlewares\Third_Party\FreeRTOS\Source\list.c;Middlewares\Third_Party\FreeRTOS\Source\queue.c;Middlewares\Third_Party\FreeRTOS\Source\stream_buffer.c;Middlewares\Third_Party\FreeRTOS\Source\tasks.c;Middlewares\Third_Party\FreeRTOS\Source\timers.c;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.c;Middlewares\Third_Party\FreeRTOS\Source\portable\MemMang\heap_4.c;Middlewares\Third_Party\FreeRTOS\Source\portable\GCC\ARM_CM4F\port.c;Drivers\CMSIS\Device\ST\STM32H7xx\Source\Templates\system_stm32h7xx.c;Core\Src\system_stm32h7xx.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_exti.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_tim.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_tim_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_adc.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_adc_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_flash.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_flash_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_gpio.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_hsem.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_mdma.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cortex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2c.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2c_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_exti.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_rcc.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_utils.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dac.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dac_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_fmc.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_nor.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_sram.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_nand.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_sdram.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_i2c.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_gpio.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_dma.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_qspi.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_delayblock.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_sdmmc.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_sd.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_sd_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_mmc.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_mmc_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_spi.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_spi_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pcd.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pcd_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_usb.c;Middlewares\Third_Party\FreeRTOS\Source\croutine.c;Middlewares\Third_Party\FreeRTOS\Source\event_groups.c;Middlewares\Third_Party\FreeRTOS\Source\list.c;Middlewares\Third_Party\FreeRTOS\Source\queue.c;Middlewares\Third_Party\FreeRTOS\Source\stream_buffer.c;Middlewares\Third_Party\FreeRTOS\Source\tasks.c;Middlewares\Third_Party\FreeRTOS\Source\timers.c;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.c;Middlewares\Third_Party\FreeRTOS\Source\portable\MemMang\heap_4.c;Middlewares\Third_Party\FreeRTOS\Source\portable\GCC\ARM_CM4F\port.c;Drivers\CMSIS\Device\ST\STM32H7xx\Source\Templates\system_stm32h7xx.c;Core\Src\system_stm32h7xx.c;;;Middlewares\Third_Party\FreeRTOS\Source\croutine.c;Middlewares\Third_Party\FreeRTOS\Source\event_groups.c;Middlewares\Third_Party\FreeRTOS\Source\list.c;Middlewares\Third_Party\FreeRTOS\Source\queue.c;Middlewares\Third_Party\FreeRTOS\Source\stream_buffer.c;Middlewares\Third_Party\FreeRTOS\Source\tasks.c;Middlewares\Third_Party\FreeRTOS\Source\timers.c;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.c;Middlewares\Third_Party\FreeRTOS\Source\portable\MemMang\heap_4.c;Middlewares\Third_Party\FreeRTOS\Source\portable\GCC\ARM_CM4F\port.c;
diff --git a/fw/Core/Inc/main.h b/fw/Core/Inc/main.h
index 28c5556..3e222c5 100644
--- a/fw/Core/Inc/main.h
+++ b/fw/Core/Inc/main.h
@@ -61,8 +61,6 @@ extern "C" {
 
 /* USER CODE END EM */
 
-void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
-
 /* Exported functions prototypes ---------------------------------------------*/
 void Error_Handler(void);
 
diff --git a/fw/Core/Inc/stm32h7xx_it.h b/fw/Core/Inc/stm32h7xx_it.h
index 8af1867..8a71416 100644
--- a/fw/Core/Inc/stm32h7xx_it.h
+++ b/fw/Core/Inc/stm32h7xx_it.h
@@ -53,6 +53,7 @@ void BusFault_Handler(void);
 void UsageFault_Handler(void);
 void DebugMon_Handler(void);
 void DMA1_Stream0_IRQHandler(void);
+void DMA1_Stream1_IRQHandler(void);
 void TIM2_IRQHandler(void);
 void SPI2_IRQHandler(void);
 void EXTI15_10_IRQHandler(void);
diff --git a/fw/Core/Src/main.c b/fw/Core/Src/main.c
index 0a7d7c6..afb6989 100644
--- a/fw/Core/Src/main.c
+++ b/fw/Core/Src/main.c
@@ -42,6 +42,7 @@
 
 /* Private variables ---------------------------------------------------------*/
 ADC_HandleTypeDef hadc1;
+DMA_HandleTypeDef hdma_adc1;
 
 DAC_HandleTypeDef hdac1;
 
@@ -51,8 +52,6 @@ MDMA_HandleTypeDef hmdma_quadspi_fifo_th;
 SPI_HandleTypeDef hspi2;
 DMA_HandleTypeDef hdma_spi2_tx;
 
-TIM_HandleTypeDef htim1;
-
 PCD_HandleTypeDef hpcd_USB_OTG_FS;
 
 SRAM_HandleTypeDef hsram1;
@@ -80,7 +79,6 @@ static void MX_FMC_Init(void);
 static void MX_I2C1_Init(void);
 static void MX_QUADSPI_Init(void);
 static void MX_SPI2_Init(void);
-static void MX_TIM1_Init(void);
 static void MX_USB_OTG_FS_PCD_Init(void);
 void StartDefaultTask(void *argument);
 
@@ -133,7 +131,6 @@ int main(void)
   MX_I2C1_Init();
   MX_QUADSPI_Init();
   MX_SPI2_Init();
-  MX_TIM1_Init();
   MX_USB_OTG_FS_PCD_Init();
   /* USER CODE BEGIN 2 */
   NVIC_SetPriority(OTG_FS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
@@ -288,15 +285,15 @@ static void MX_ADC1_Init(void)
   hadc1.Instance = ADC1;
   hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV2;
   hadc1.Init.Resolution = ADC_RESOLUTION_16B;
-  hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE;
+  hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE;
   hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
   hadc1.Init.LowPowerAutoWait = DISABLE;
   hadc1.Init.ContinuousConvMode = DISABLE;
-  hadc1.Init.NbrOfConversion = 1;
+  hadc1.Init.NbrOfConversion = 6;
   hadc1.Init.DiscontinuousConvMode = DISABLE;
   hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
   hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
-  hadc1.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR;
+  hadc1.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DMA_ONESHOT;
   hadc1.Init.Overrun = ADC_OVR_DATA_PRESERVED;
   hadc1.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE;
   hadc1.Init.OversamplingMode = DISABLE;
@@ -316,9 +313,9 @@ static void MX_ADC1_Init(void)
 
   /** Configure Regular Channel
   */
-  sConfig.Channel = ADC_CHANNEL_7;
+  sConfig.Channel = ADC_CHANNEL_3;
   sConfig.Rank = ADC_REGULAR_RANK_1;
-  sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5;
+  sConfig.SamplingTime = ADC_SAMPLETIME_8CYCLES_5;
   sConfig.SingleDiff = ADC_SINGLE_ENDED;
   sConfig.OffsetNumber = ADC_OFFSET_NONE;
   sConfig.Offset = 0;
@@ -327,6 +324,51 @@ static void MX_ADC1_Init(void)
   {
     Error_Handler();
   }
+
+  /** Configure Regular Channel
+  */
+  sConfig.Channel = ADC_CHANNEL_4;
+  sConfig.Rank = ADC_REGULAR_RANK_2;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /** Configure Regular Channel
+  */
+  sConfig.Channel = ADC_CHANNEL_5;
+  sConfig.Rank = ADC_REGULAR_RANK_3;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /** Configure Regular Channel
+  */
+  sConfig.Channel = ADC_CHANNEL_7;
+  sConfig.Rank = ADC_REGULAR_RANK_4;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /** Configure Regular Channel
+  */
+  sConfig.Channel = ADC_CHANNEL_8;
+  sConfig.Rank = ADC_REGULAR_RANK_5;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /** Configure Regular Channel
+  */
+  sConfig.Channel = ADC_CHANNEL_9;
+  sConfig.Rank = ADC_REGULAR_RANK_6;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
   /* USER CODE BEGIN ADC1_Init 2 */
 
   /* USER CODE END ADC1_Init 2 */
@@ -533,91 +575,6 @@ static void MX_SPI2_Init(void)
 
 }
 
-/**
-  * @brief TIM1 Initialization Function
-  * @param None
-  * @retval None
-  */
-static void MX_TIM1_Init(void)
-{
-
-  /* USER CODE BEGIN TIM1_Init 0 */
-
-  /* USER CODE END TIM1_Init 0 */
-
-  TIM_ClockConfigTypeDef sClockSourceConfig = {0};
-  TIM_MasterConfigTypeDef sMasterConfig = {0};
-  TIM_OC_InitTypeDef sConfigOC = {0};
-  TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0};
-
-  /* USER CODE BEGIN TIM1_Init 1 */
-
-  /* USER CODE END TIM1_Init 1 */
-  htim1.Instance = TIM1;
-  htim1.Init.Prescaler = 16;
-  htim1.Init.CounterMode = TIM_COUNTERMODE_UP;
-  htim1.Init.Period = 255;
-  htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
-  htim1.Init.RepetitionCounter = 0;
-  htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
-  if (HAL_TIM_Base_Init(&htim1) != HAL_OK)
-  {
-    Error_Handler();
-  }
-  sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
-  if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK)
-  {
-    Error_Handler();
-  }
-  if (HAL_TIM_PWM_Init(&htim1) != HAL_OK)
-  {
-    Error_Handler();
-  }
-  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
-  sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET;
-  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
-  if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK)
-  {
-    Error_Handler();
-  }
-  sConfigOC.OCMode = TIM_OCMODE_PWM1;
-  sConfigOC.Pulse = 127;
-  sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
-  sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH;
-  sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
-  sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET;
-  sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET;
-  if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)
-  {
-    Error_Handler();
-  }
-  sConfigOC.Pulse = 0;
-  if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_4) != HAL_OK)
-  {
-    Error_Handler();
-  }
-  sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE;
-  sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE;
-  sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF;
-  sBreakDeadTimeConfig.DeadTime = 0;
-  sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE;
-  sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH;
-  sBreakDeadTimeConfig.BreakFilter = 0;
-  sBreakDeadTimeConfig.Break2State = TIM_BREAK2_DISABLE;
-  sBreakDeadTimeConfig.Break2Polarity = TIM_BREAK2POLARITY_HIGH;
-  sBreakDeadTimeConfig.Break2Filter = 0;
-  sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE;
-  if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK)
-  {
-    Error_Handler();
-  }
-  /* USER CODE BEGIN TIM1_Init 2 */
-
-  /* USER CODE END TIM1_Init 2 */
-  HAL_TIM_MspPostInit(&htim1);
-
-}
-
 /**
   * @brief USB_OTG_FS Initialization Function
   * @param None
@@ -667,6 +624,9 @@ static void MX_DMA_Init(void)
   /* DMA1_Stream0_IRQn interrupt configuration */
   HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 5, 0);
   HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn);
+  /* DMA1_Stream1_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Stream1_IRQn, 5, 0);
+  HAL_NVIC_EnableIRQ(DMA1_Stream1_IRQn);
 
 }
 
@@ -779,6 +739,12 @@ static void MX_GPIO_Init(void)
   /*Configure GPIO pin Output Level */
   HAL_GPIO_WritePin(GPIOD, GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_6, GPIO_PIN_RESET);
 
+  /*Configure GPIO pins : PE3 PE4 */
+  GPIO_InitStruct.Pin = GPIO_PIN_3|GPIO_PIN_4;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_PULLDOWN;
+  HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
+
   /*Configure GPIO pins : PA2 PA3 PA10 */
   GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_10;
   GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
diff --git a/fw/Core/Src/stm32h7xx_hal_msp.c b/fw/Core/Src/stm32h7xx_hal_msp.c
index 71db1dc..c4edff8 100644
--- a/fw/Core/Src/stm32h7xx_hal_msp.c
+++ b/fw/Core/Src/stm32h7xx_hal_msp.c
@@ -23,6 +23,8 @@
 /* USER CODE BEGIN Includes */
 
 /* USER CODE END Includes */
+extern DMA_HandleTypeDef hdma_adc1;
+
 extern MDMA_HandleTypeDef hmdma_quadspi_fifo_th;
 
 extern DMA_HandleTypeDef hdma_spi2_tx;
@@ -60,9 +62,7 @@ extern DMA_HandleTypeDef hdma_spi2_tx;
 /* USER CODE BEGIN 0 */
 
 /* USER CODE END 0 */
-
-void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
-                    /**
+/**
   * Initializes the Global MSP.
   */
 void HAL_MspInit(void)
@@ -145,6 +145,25 @@ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
     GPIO_InitStruct.Pull = GPIO_NOPULL;
     HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 
+    /* ADC1 DMA Init */
+    /* ADC1 Init */
+    hdma_adc1.Instance = DMA1_Stream1;
+    hdma_adc1.Init.Request = DMA_REQUEST_ADC1;
+    hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY;
+    hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE;
+    hdma_adc1.Init.MemInc = DMA_MINC_ENABLE;
+    hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
+    hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
+    hdma_adc1.Init.Mode = DMA_NORMAL;
+    hdma_adc1.Init.Priority = DMA_PRIORITY_LOW;
+    hdma_adc1.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
+    if (HAL_DMA_Init(&hdma_adc1) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc1);
+
   /* USER CODE BEGIN ADC1_MspInit 1 */
 
   /* USER CODE END ADC1_MspInit 1 */
@@ -183,6 +202,8 @@ void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
 
     HAL_GPIO_DeInit(GPIOB, GPIO_PIN_0|GPIO_PIN_1);
 
+    /* ADC1 DMA DeInit */
+    HAL_DMA_DeInit(hadc->DMA_Handle);
   /* USER CODE BEGIN ADC1_MspDeInit 1 */
 
   /* USER CODE END ADC1_MspDeInit 1 */
@@ -532,78 +553,6 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi)
 
 }
 
-/**
-* @brief TIM_Base MSP Initialization
-* This function configures the hardware resources used in this example
-* @param htim_base: TIM_Base handle pointer
-* @retval None
-*/
-void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
-{
-  if(htim_base->Instance==TIM1)
-  {
-  /* USER CODE BEGIN TIM1_MspInit 0 */
-
-  /* USER CODE END TIM1_MspInit 0 */
-    /* Peripheral clock enable */
-    __HAL_RCC_TIM1_CLK_ENABLE();
-  /* USER CODE BEGIN TIM1_MspInit 1 */
-
-  /* USER CODE END TIM1_MspInit 1 */
-
-  }
-
-}
-
-void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
-{
-  GPIO_InitTypeDef GPIO_InitStruct = {0};
-  if(htim->Instance==TIM1)
-  {
-  /* USER CODE BEGIN TIM1_MspPostInit 0 */
-
-  /* USER CODE END TIM1_MspPostInit 0 */
-
-    __HAL_RCC_GPIOE_CLK_ENABLE();
-    /**TIM1 GPIO Configuration
-    PE13     ------> TIM1_CH3
-    PE14     ------> TIM1_CH4
-    */
-    GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_14;
-    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-    GPIO_InitStruct.Pull = GPIO_NOPULL;
-    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
-    GPIO_InitStruct.Alternate = GPIO_AF1_TIM1;
-    HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
-
-  /* USER CODE BEGIN TIM1_MspPostInit 1 */
-
-  /* USER CODE END TIM1_MspPostInit 1 */
-  }
-
-}
-/**
-* @brief TIM_Base MSP De-Initialization
-* This function freeze the hardware resources used in this example
-* @param htim_base: TIM_Base handle pointer
-* @retval None
-*/
-void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base)
-{
-  if(htim_base->Instance==TIM1)
-  {
-  /* USER CODE BEGIN TIM1_MspDeInit 0 */
-
-  /* USER CODE END TIM1_MspDeInit 0 */
-    /* Peripheral clock disable */
-    __HAL_RCC_TIM1_CLK_DISABLE();
-  /* USER CODE BEGIN TIM1_MspDeInit 1 */
-
-  /* USER CODE END TIM1_MspDeInit 1 */
-  }
-
-}
-
 /**
 * @brief PCD MSP Initialization
 * This function configures the hardware resources used in this example
diff --git a/fw/Core/Src/stm32h7xx_it.c b/fw/Core/Src/stm32h7xx_it.c
index b1220b0..c651cf0 100644
--- a/fw/Core/Src/stm32h7xx_it.c
+++ b/fw/Core/Src/stm32h7xx_it.c
@@ -56,6 +56,7 @@
 /* USER CODE END 0 */
 
 /* External variables --------------------------------------------------------*/
+extern DMA_HandleTypeDef hdma_adc1;
 extern MDMA_HandleTypeDef hmdma_quadspi_fifo_th;
 extern QSPI_HandleTypeDef hqspi;
 extern DMA_HandleTypeDef hdma_spi2_tx;
@@ -179,6 +180,20 @@ void DMA1_Stream0_IRQHandler(void)
   /* USER CODE END DMA1_Stream0_IRQn 1 */
 }
 
+/**
+  * @brief This function handles DMA1 stream1 global interrupt.
+  */
+void DMA1_Stream1_IRQHandler(void)
+{
+  /* USER CODE BEGIN DMA1_Stream1_IRQn 0 */
+
+  /* USER CODE END DMA1_Stream1_IRQn 0 */
+  HAL_DMA_IRQHandler(&hdma_adc1);
+  /* USER CODE BEGIN DMA1_Stream1_IRQn 1 */
+
+  /* USER CODE END DMA1_Stream1_IRQn 1 */
+}
+
 /**
   * @brief This function handles TIM2 global interrupt.
   */
diff --git a/fw/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_tim.h b/fw/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_tim.h
deleted file mode 100644
index 050f738..0000000
--- a/fw/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_tim.h
+++ /dev/null
@@ -1,5213 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32h7xx_ll_tim.h
-  * @author  MCD Application Team
-  * @brief   Header file of TIM LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_LL_TIM_H
-#define __STM32H7xx_LL_TIM_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx.h"
-
-/** @addtogroup STM32H7xx_LL_Driver
-  * @{
-  */
-
-#if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM23) || defined (TIM24)
-
-/** @defgroup TIM_LL TIM
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup TIM_LL_Private_Variables TIM Private Variables
-  * @{
-  */
-static const uint8_t OFFSET_TAB_CCMRx[] =
-{
-  0x00U,   /* 0: TIMx_CH1  */
-  0x00U,   /* 1: TIMx_CH1N */
-  0x00U,   /* 2: TIMx_CH2  */
-  0x00U,   /* 3: TIMx_CH2N */
-  0x04U,   /* 4: TIMx_CH3  */
-  0x04U,   /* 5: TIMx_CH3N */
-  0x04U,   /* 6: TIMx_CH4  */
-  0x3CU,   /* 7: TIMx_CH5  */
-  0x3CU    /* 8: TIMx_CH6  */
-};
-
-static const uint8_t SHIFT_TAB_OCxx[] =
-{
-  0U,            /* 0: OC1M, OC1FE, OC1PE */
-  0U,            /* 1: - NA */
-  8U,            /* 2: OC2M, OC2FE, OC2PE */
-  0U,            /* 3: - NA */
-  0U,            /* 4: OC3M, OC3FE, OC3PE */
-  0U,            /* 5: - NA */
-  8U,            /* 6: OC4M, OC4FE, OC4PE */
-  0U,            /* 7: OC5M, OC5FE, OC5PE */
-  8U             /* 8: OC6M, OC6FE, OC6PE */
-};
-
-static const uint8_t SHIFT_TAB_ICxx[] =
-{
-  0U,            /* 0: CC1S, IC1PSC, IC1F */
-  0U,            /* 1: - NA */
-  8U,            /* 2: CC2S, IC2PSC, IC2F */
-  0U,            /* 3: - NA */
-  0U,            /* 4: CC3S, IC3PSC, IC3F */
-  0U,            /* 5: - NA */
-  8U,            /* 6: CC4S, IC4PSC, IC4F */
-  0U,            /* 7: - NA */
-  0U             /* 8: - NA */
-};
-
-static const uint8_t SHIFT_TAB_CCxP[] =
-{
-  0U,            /* 0: CC1P */
-  2U,            /* 1: CC1NP */
-  4U,            /* 2: CC2P */
-  6U,            /* 3: CC2NP */
-  8U,            /* 4: CC3P */
-  10U,           /* 5: CC3NP */
-  12U,           /* 6: CC4P */
-  16U,           /* 7: CC5P */
-  20U            /* 8: CC6P */
-};
-
-static const uint8_t SHIFT_TAB_OISx[] =
-{
-  0U,            /* 0: OIS1 */
-  1U,            /* 1: OIS1N */
-  2U,            /* 2: OIS2 */
-  3U,            /* 3: OIS2N */
-  4U,            /* 4: OIS3 */
-  5U,            /* 5: OIS3N */
-  6U,            /* 6: OIS4 */
-  8U,            /* 7: OIS5 */
-  10U            /* 8: OIS6 */
-};
-/**
-  * @}
-  */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup TIM_LL_Private_Constants TIM Private Constants
-  * @{
-  */
-
-#if   defined(TIM_BREAK_INPUT_SUPPORT)
-/* Defines used for the bit position in the register and perform offsets */
-#define TIM_POSITION_BRK_SOURCE            (POSITION_VAL(Source) & 0x1FUL)
-
-/* Generic bit definitions for TIMx_AF1 register */
-#define TIMx_AF1_BKINP     TIM1_AF1_BKINP     /*!< BRK BKIN input polarity */
-#define TIMx_AF1_ETRSEL    TIM1_AF1_ETRSEL    /*!< TIMx ETR source selection */
-#endif /* TIM_BREAK_INPUT_SUPPORT */
-
-
-/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
-#define DT_DELAY_1 ((uint8_t)0x7F)
-#define DT_DELAY_2 ((uint8_t)0x3F)
-#define DT_DELAY_3 ((uint8_t)0x1F)
-#define DT_DELAY_4 ((uint8_t)0x1F)
-
-/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
-#define DT_RANGE_1 ((uint8_t)0x00)
-#define DT_RANGE_2 ((uint8_t)0x80)
-#define DT_RANGE_3 ((uint8_t)0xC0)
-#define DT_RANGE_4 ((uint8_t)0xE0)
-
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup TIM_LL_Private_Macros TIM Private Macros
-  * @{
-  */
-/** @brief  Convert channel id into channel index.
-  * @param  __CHANNEL__ This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH1N
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH2N
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH3N
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  *         @arg @ref LL_TIM_CHANNEL_CH5
-  *         @arg @ref LL_TIM_CHANNEL_CH6
-  * @retval none
-  */
-#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
-  (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
-   ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
-   ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
-   ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
-   ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
-   ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
-   ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
-   ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U)
-
-/** @brief  Calculate the deadtime sampling period(in ps).
-  * @param  __TIMCLK__ timer input clock frequency (in Hz).
-  * @param  __CKD__ This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
-  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
-  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
-  * @retval none
-  */
-#define TIM_CALC_DTS(__TIMCLK__, __CKD__)                                                        \
-  (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__))         : \
-   ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
-   ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
-/**
-  * @}
-  */
-
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
-  * @{
-  */
-
-/**
-  * @brief  TIM Time Base configuration structure definition.
-  */
-typedef struct
-{
-  uint16_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
-                                   This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
-
-                                   This feature can be modified afterwards using unitary function
-                                   @ref LL_TIM_SetPrescaler().*/
-
-  uint32_t CounterMode;       /*!< Specifies the counter mode.
-                                   This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
-
-                                   This feature can be modified afterwards using unitary function
-                                   @ref LL_TIM_SetCounterMode().*/
-
-  uint32_t Autoreload;        /*!< Specifies the auto reload value to be loaded into the active
-                                   Auto-Reload Register at the next update event.
-                                   This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
-                                   Some timer instances may support 32 bits counters. In that case this parameter must
-                                   be a number between 0x0000 and 0xFFFFFFFF.
-
-                                   This feature can be modified afterwards using unitary function
-                                   @ref LL_TIM_SetAutoReload().*/
-
-  uint32_t ClockDivision;     /*!< Specifies the clock division.
-                                   This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
-
-                                   This feature can be modified afterwards using unitary function
-                                   @ref LL_TIM_SetClockDivision().*/
-
-  uint32_t RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter
-                                   reaches zero, an update event is generated and counting restarts
-                                   from the RCR value (N).
-                                   This means in PWM mode that (N+1) corresponds to:
-                                      - the number of PWM periods in edge-aligned mode
-                                      - the number of half PWM period in center-aligned mode
-                                   GP timers: this parameter must be a number between Min_Data = 0x00 and
-                                   Max_Data = 0xFF.
-                                   Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
-                                   Max_Data = 0xFFFF.
-
-                                   This feature can be modified afterwards using unitary function
-                                   @ref LL_TIM_SetRepetitionCounter().*/
-} LL_TIM_InitTypeDef;
-
-/**
-  * @brief  TIM Output Compare configuration structure definition.
-  */
-typedef struct
-{
-  uint32_t OCMode;        /*!< Specifies the output mode.
-                               This parameter can be a value of @ref TIM_LL_EC_OCMODE.
-
-                               This feature can be modified afterwards using unitary function
-                               @ref LL_TIM_OC_SetMode().*/
-
-  uint32_t OCState;       /*!< Specifies the TIM Output Compare state.
-                               This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
-
-                               This feature can be modified afterwards using unitary functions
-                               @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
-
-  uint32_t OCNState;      /*!< Specifies the TIM complementary Output Compare state.
-                               This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
-
-                               This feature can be modified afterwards using unitary functions
-                               @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
-
-  uint32_t CompareValue;  /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
-                               This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
-
-                               This feature can be modified afterwards using unitary function
-                               LL_TIM_OC_SetCompareCHx (x=1..6).*/
-
-  uint32_t OCPolarity;    /*!< Specifies the output polarity.
-                               This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
-
-                               This feature can be modified afterwards using unitary function
-                               @ref LL_TIM_OC_SetPolarity().*/
-
-  uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
-                               This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
-
-                               This feature can be modified afterwards using unitary function
-                               @ref LL_TIM_OC_SetPolarity().*/
-
-
-  uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
-                               This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
-
-                               This feature can be modified afterwards using unitary function
-                               @ref LL_TIM_OC_SetIdleState().*/
-
-  uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
-                               This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
-
-                               This feature can be modified afterwards using unitary function
-                               @ref LL_TIM_OC_SetIdleState().*/
-} LL_TIM_OC_InitTypeDef;
-
-/**
-  * @brief  TIM Input Capture configuration structure definition.
-  */
-
-typedef struct
-{
-
-  uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
-                               This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
-
-                               This feature can be modified afterwards using unitary function
-                               @ref LL_TIM_IC_SetPolarity().*/
-
-  uint32_t ICActiveInput; /*!< Specifies the input.
-                               This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
-
-                               This feature can be modified afterwards using unitary function
-                               @ref LL_TIM_IC_SetActiveInput().*/
-
-  uint32_t ICPrescaler;   /*!< Specifies the Input Capture Prescaler.
-                               This parameter can be a value of @ref TIM_LL_EC_ICPSC.
-
-                               This feature can be modified afterwards using unitary function
-                               @ref LL_TIM_IC_SetPrescaler().*/
-
-  uint32_t ICFilter;      /*!< Specifies the input capture filter.
-                               This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
-
-                               This feature can be modified afterwards using unitary function
-                               @ref LL_TIM_IC_SetFilter().*/
-} LL_TIM_IC_InitTypeDef;
-
-
-/**
-  * @brief  TIM Encoder interface configuration structure definition.
-  */
-typedef struct
-{
-  uint32_t EncoderMode;     /*!< Specifies the encoder resolution (x2 or x4).
-                                 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
-
-                                 This feature can be modified afterwards using unitary function
-                                 @ref LL_TIM_SetEncoderMode().*/
-
-  uint32_t IC1Polarity;     /*!< Specifies the active edge of TI1 input.
-                                 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
-
-                                 This feature can be modified afterwards using unitary function
-                                 @ref LL_TIM_IC_SetPolarity().*/
-
-  uint32_t IC1ActiveInput;  /*!< Specifies the TI1 input source
-                                 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
-
-                                 This feature can be modified afterwards using unitary function
-                                 @ref LL_TIM_IC_SetActiveInput().*/
-
-  uint32_t IC1Prescaler;    /*!< Specifies the TI1 input prescaler value.
-                                 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
-
-                                 This feature can be modified afterwards using unitary function
-                                 @ref LL_TIM_IC_SetPrescaler().*/
-
-  uint32_t IC1Filter;       /*!< Specifies the TI1 input filter.
-                                 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
-
-                                 This feature can be modified afterwards using unitary function
-                                 @ref LL_TIM_IC_SetFilter().*/
-
-  uint32_t IC2Polarity;      /*!< Specifies the active edge of TI2 input.
-                                 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
-
-                                 This feature can be modified afterwards using unitary function
-                                 @ref LL_TIM_IC_SetPolarity().*/
-
-  uint32_t IC2ActiveInput;  /*!< Specifies the TI2 input source
-                                 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
-
-                                 This feature can be modified afterwards using unitary function
-                                 @ref LL_TIM_IC_SetActiveInput().*/
-
-  uint32_t IC2Prescaler;    /*!< Specifies the TI2 input prescaler value.
-                                 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
-
-                                 This feature can be modified afterwards using unitary function
-                                 @ref LL_TIM_IC_SetPrescaler().*/
-
-  uint32_t IC2Filter;       /*!< Specifies the TI2 input filter.
-                                 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
-
-                                 This feature can be modified afterwards using unitary function
-                                 @ref LL_TIM_IC_SetFilter().*/
-
-} LL_TIM_ENCODER_InitTypeDef;
-
-/**
-  * @brief  TIM Hall sensor interface configuration structure definition.
-  */
-typedef struct
-{
-
-  uint32_t IC1Polarity;        /*!< Specifies the active edge of TI1 input.
-                                    This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
-
-                                    This feature can be modified afterwards using unitary function
-                                    @ref LL_TIM_IC_SetPolarity().*/
-
-  uint32_t IC1Prescaler;       /*!< Specifies the TI1 input prescaler value.
-                                    Prescaler must be set to get a maximum counter period longer than the
-                                    time interval between 2 consecutive changes on the Hall inputs.
-                                    This parameter can be a value of @ref TIM_LL_EC_ICPSC.
-
-                                    This feature can be modified afterwards using unitary function
-                                    @ref LL_TIM_IC_SetPrescaler().*/
-
-  uint32_t IC1Filter;          /*!< Specifies the TI1 input filter.
-                                    This parameter can be a value of
-                                    @ref TIM_LL_EC_IC_FILTER.
-
-                                    This feature can be modified afterwards using unitary function
-                                    @ref LL_TIM_IC_SetFilter().*/
-
-  uint32_t CommutationDelay;   /*!< Specifies the compare value to be loaded into the Capture Compare Register.
-                                    A positive pulse (TRGO event) is generated with a programmable delay every time
-                                    a change occurs on the Hall inputs.
-                                    This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
-
-                                    This feature can be modified afterwards using unitary function
-                                    @ref LL_TIM_OC_SetCompareCH2().*/
-} LL_TIM_HALLSENSOR_InitTypeDef;
-
-/**
-  * @brief  BDTR (Break and Dead Time) structure definition
-  */
-typedef struct
-{
-  uint32_t OSSRState;            /*!< Specifies the Off-State selection used in Run mode.
-                                      This parameter can be a value of @ref TIM_LL_EC_OSSR
-
-                                      This feature can be modified afterwards using unitary function
-                                      @ref LL_TIM_SetOffStates()
-
-                                      @note This bit-field cannot be modified as long as LOCK level 2 has been
-                                       programmed. */
-
-  uint32_t OSSIState;            /*!< Specifies the Off-State used in Idle state.
-                                      This parameter can be a value of @ref TIM_LL_EC_OSSI
-
-                                      This feature can be modified afterwards using unitary function
-                                      @ref LL_TIM_SetOffStates()
-
-                                      @note This bit-field cannot be modified as long as LOCK level 2 has been
-                                      programmed. */
-
-  uint32_t LockLevel;            /*!< Specifies the LOCK level parameters.
-                                      This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
-
-                                      @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR
-                                      register has been written, their content is frozen until the next reset.*/
-
-  uint8_t DeadTime;              /*!< Specifies the delay time between the switching-off and the
-                                      switching-on of the outputs.
-                                      This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
-
-                                      This feature can be modified afterwards using unitary function
-                                      @ref LL_TIM_OC_SetDeadTime()
-
-                                      @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been
-                                       programmed. */
-
-  uint16_t BreakState;           /*!< Specifies whether the TIM Break input is enabled or not.
-                                      This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
-
-                                      This feature can be modified afterwards using unitary functions
-                                      @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
-
-                                      @note This bit-field can not be modified as long as LOCK level 1 has been
-                                      programmed. */
-
-  uint32_t BreakPolarity;        /*!< Specifies the TIM Break Input pin polarity.
-                                      This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
-
-                                      This feature can be modified afterwards using unitary function
-                                      @ref LL_TIM_ConfigBRK()
-
-                                      @note This bit-field can not be modified as long as LOCK level 1 has been
-                                      programmed. */
-
-  uint32_t BreakFilter;          /*!< Specifies the TIM Break Filter.
-                                      This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
-
-                                      This feature can be modified afterwards using unitary function
-                                      @ref LL_TIM_ConfigBRK()
-
-                                      @note This bit-field can not be modified as long as LOCK level 1 has been
-                                      programmed. */
-
-#if defined(TIM_BDTR_BKBID)
-  uint32_t BreakAFMode;           /*!< Specifies the alternate function mode of the break input.
-                                      This parameter can be a value of @ref TIM_LL_EC_BREAK_AFMODE
-
-                                      This feature can be modified afterwards using unitary functions
-                                      @ref LL_TIM_ConfigBRK()
-
-                                      @note Bidirectional break input is only supported by advanced timers instances.
-
-                                      @note This bit-field can not be modified as long as LOCK level 1 has been
-                                      programmed. */
-
-#endif /*TIM_BDTR_BKBID */
-  uint32_t Break2State;          /*!< Specifies whether the TIM Break2 input is enabled or not.
-                                      This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
-
-                                      This feature can be modified afterwards using unitary functions
-                                      @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
-
-                                      @note This bit-field can not be modified as long as LOCK level 1 has been
-                                      programmed. */
-
-  uint32_t Break2Polarity;        /*!< Specifies the TIM Break2 Input pin polarity.
-                                      This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
-
-                                      This feature can be modified afterwards using unitary function
-                                      @ref LL_TIM_ConfigBRK2()
-
-                                      @note This bit-field can not be modified as long as LOCK level 1 has been
-                                      programmed. */
-
-  uint32_t Break2Filter;          /*!< Specifies the TIM Break2 Filter.
-                                      This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
-
-                                      This feature can be modified afterwards using unitary function
-                                      @ref LL_TIM_ConfigBRK2()
-
-                                      @note This bit-field can not be modified as long as LOCK level 1 has been
-                                      programmed. */
-
-#if defined(TIM_BDTR_BKBID)
-  uint32_t Break2AFMode;          /*!< Specifies the alternate function mode of the break2 input.
-                                      This parameter can be a value of @ref TIM_LL_EC_BREAK2_AFMODE
-
-                                      This feature can be modified afterwards using unitary functions
-                                      @ref LL_TIM_ConfigBRK2()
-
-                                      @note Bidirectional break input is only supported by advanced timers instances.
-
-                                      @note This bit-field can not be modified as long as LOCK level 1 has been
-                                      programmed. */
-
-#endif /*TIM_BDTR_BKBID */
-  uint32_t AutomaticOutput;      /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
-                                      This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
-
-                                      This feature can be modified afterwards using unitary functions
-                                      @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
-
-                                      @note This bit-field can not be modified as long as LOCK level 1 has been
-                                      programmed. */
-} LL_TIM_BDTR_InitTypeDef;
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
-  * @{
-  */
-
-/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
-  * @brief    Flags defines which can be used with LL_TIM_ReadReg function.
-  * @{
-  */
-#define LL_TIM_SR_UIF                          TIM_SR_UIF           /*!< Update interrupt flag */
-#define LL_TIM_SR_CC1IF                        TIM_SR_CC1IF         /*!< Capture/compare 1 interrupt flag */
-#define LL_TIM_SR_CC2IF                        TIM_SR_CC2IF         /*!< Capture/compare 2 interrupt flag */
-#define LL_TIM_SR_CC3IF                        TIM_SR_CC3IF         /*!< Capture/compare 3 interrupt flag */
-#define LL_TIM_SR_CC4IF                        TIM_SR_CC4IF         /*!< Capture/compare 4 interrupt flag */
-#define LL_TIM_SR_CC5IF                        TIM_SR_CC5IF         /*!< Capture/compare 5 interrupt flag */
-#define LL_TIM_SR_CC6IF                        TIM_SR_CC6IF         /*!< Capture/compare 6 interrupt flag */
-#define LL_TIM_SR_COMIF                        TIM_SR_COMIF         /*!< COM interrupt flag */
-#define LL_TIM_SR_TIF                          TIM_SR_TIF           /*!< Trigger interrupt flag */
-#define LL_TIM_SR_BIF                          TIM_SR_BIF           /*!< Break interrupt flag */
-#define LL_TIM_SR_B2IF                         TIM_SR_B2IF          /*!< Second break interrupt flag */
-#define LL_TIM_SR_CC1OF                        TIM_SR_CC1OF         /*!< Capture/Compare 1 overcapture flag */
-#define LL_TIM_SR_CC2OF                        TIM_SR_CC2OF         /*!< Capture/Compare 2 overcapture flag */
-#define LL_TIM_SR_CC3OF                        TIM_SR_CC3OF         /*!< Capture/Compare 3 overcapture flag */
-#define LL_TIM_SR_CC4OF                        TIM_SR_CC4OF         /*!< Capture/Compare 4 overcapture flag */
-#define LL_TIM_SR_SBIF                         TIM_SR_SBIF          /*!< System Break interrupt flag  */
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
-  * @{
-  */
-#define LL_TIM_BREAK_DISABLE            0x00000000U             /*!< Break function disabled */
-#define LL_TIM_BREAK_ENABLE             TIM_BDTR_BKE            /*!< Break function enabled */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
-  * @{
-  */
-#define LL_TIM_BREAK2_DISABLE            0x00000000U              /*!< Break2 function disabled */
-#define LL_TIM_BREAK2_ENABLE             TIM_BDTR_BK2E            /*!< Break2 function enabled */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
-  * @{
-  */
-#define LL_TIM_AUTOMATICOUTPUT_DISABLE         0x00000000U             /*!< MOE can be set only by software */
-#define LL_TIM_AUTOMATICOUTPUT_ENABLE          TIM_BDTR_AOE            /*!< MOE can be set by software or automatically at the next update event */
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/** @defgroup TIM_LL_EC_IT IT Defines
-  * @brief    IT defines which can be used with LL_TIM_ReadReg and  LL_TIM_WriteReg functions.
-  * @{
-  */
-#define LL_TIM_DIER_UIE                        TIM_DIER_UIE         /*!< Update interrupt enable */
-#define LL_TIM_DIER_CC1IE                      TIM_DIER_CC1IE       /*!< Capture/compare 1 interrupt enable */
-#define LL_TIM_DIER_CC2IE                      TIM_DIER_CC2IE       /*!< Capture/compare 2 interrupt enable */
-#define LL_TIM_DIER_CC3IE                      TIM_DIER_CC3IE       /*!< Capture/compare 3 interrupt enable */
-#define LL_TIM_DIER_CC4IE                      TIM_DIER_CC4IE       /*!< Capture/compare 4 interrupt enable */
-#define LL_TIM_DIER_COMIE                      TIM_DIER_COMIE       /*!< COM interrupt enable */
-#define LL_TIM_DIER_TIE                        TIM_DIER_TIE         /*!< Trigger interrupt enable */
-#define LL_TIM_DIER_BIE                        TIM_DIER_BIE         /*!< Break interrupt enable */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
-  * @{
-  */
-#define LL_TIM_UPDATESOURCE_REGULAR            0x00000000U          /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
-#define LL_TIM_UPDATESOURCE_COUNTER            TIM_CR1_URS          /*!< Only counter overflow/underflow generates an update request */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
-  * @{
-  */
-#define LL_TIM_ONEPULSEMODE_SINGLE             TIM_CR1_OPM          /*!< Counter stops counting at the next update event */
-#define LL_TIM_ONEPULSEMODE_REPETITIVE         0x00000000U          /*!< Counter is not stopped at update event */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
-  * @{
-  */
-#define LL_TIM_COUNTERMODE_UP                  0x00000000U          /*!< Counter used as upcounter */
-#define LL_TIM_COUNTERMODE_DOWN                TIM_CR1_DIR          /*!< Counter used as downcounter */
-#define LL_TIM_COUNTERMODE_CENTER_DOWN         TIM_CR1_CMS_0        /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting down. */
-#define LL_TIM_COUNTERMODE_CENTER_UP           TIM_CR1_CMS_1        /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up */
-#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN      TIM_CR1_CMS          /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up or down. */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
-  * @{
-  */
-#define LL_TIM_CLOCKDIVISION_DIV1              0x00000000U          /*!< tDTS=tCK_INT */
-#define LL_TIM_CLOCKDIVISION_DIV2              TIM_CR1_CKD_0        /*!< tDTS=2*tCK_INT */
-#define LL_TIM_CLOCKDIVISION_DIV4              TIM_CR1_CKD_1        /*!< tDTS=4*tCK_INT */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
-  * @{
-  */
-#define LL_TIM_COUNTERDIRECTION_UP             0x00000000U          /*!< Timer counter counts up */
-#define LL_TIM_COUNTERDIRECTION_DOWN           TIM_CR1_DIR          /*!< Timer counter counts down */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare  Update Source
-  * @{
-  */
-#define LL_TIM_CCUPDATESOURCE_COMG_ONLY        0x00000000U          /*!< Capture/compare control bits are updated by setting the COMG bit only */
-#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI    TIM_CR2_CCUS         /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
-  * @{
-  */
-#define LL_TIM_CCDMAREQUEST_CC                 0x00000000U          /*!< CCx DMA request sent when CCx event occurs */
-#define LL_TIM_CCDMAREQUEST_UPDATE             TIM_CR2_CCDS         /*!< CCx DMA requests sent when update event occurs */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
-  * @{
-  */
-#define LL_TIM_LOCKLEVEL_OFF                   0x00000000U          /*!< LOCK OFF - No bit is write protected */
-#define LL_TIM_LOCKLEVEL_1                     TIM_BDTR_LOCK_0      /*!< LOCK Level 1 */
-#define LL_TIM_LOCKLEVEL_2                     TIM_BDTR_LOCK_1      /*!< LOCK Level 2 */
-#define LL_TIM_LOCKLEVEL_3                     TIM_BDTR_LOCK        /*!< LOCK Level 3 */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_CHANNEL Channel
-  * @{
-  */
-#define LL_TIM_CHANNEL_CH1                     TIM_CCER_CC1E     /*!< Timer input/output channel 1 */
-#define LL_TIM_CHANNEL_CH1N                    TIM_CCER_CC1NE    /*!< Timer complementary output channel 1 */
-#define LL_TIM_CHANNEL_CH2                     TIM_CCER_CC2E     /*!< Timer input/output channel 2 */
-#define LL_TIM_CHANNEL_CH2N                    TIM_CCER_CC2NE    /*!< Timer complementary output channel 2 */
-#define LL_TIM_CHANNEL_CH3                     TIM_CCER_CC3E     /*!< Timer input/output channel 3 */
-#define LL_TIM_CHANNEL_CH3N                    TIM_CCER_CC3NE    /*!< Timer complementary output channel 3 */
-#define LL_TIM_CHANNEL_CH4                     TIM_CCER_CC4E     /*!< Timer input/output channel 4 */
-#define LL_TIM_CHANNEL_CH5                     TIM_CCER_CC5E     /*!< Timer output channel 5 */
-#define LL_TIM_CHANNEL_CH6                     TIM_CCER_CC6E     /*!< Timer output channel 6 */
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
-  * @{
-  */
-#define LL_TIM_OCSTATE_DISABLE                 0x00000000U             /*!< OCx is not active */
-#define LL_TIM_OCSTATE_ENABLE                  TIM_CCER_CC1E           /*!< OCx signal is output on the corresponding output pin */
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/** Legacy definitions for compatibility purpose
-@cond 0
-  */
-#define LL_TIM_OCMODE_ASSYMETRIC_PWM1 LL_TIM_OCMODE_ASYMMETRIC_PWM1
-#define LL_TIM_OCMODE_ASSYMETRIC_PWM2 LL_TIM_OCMODE_ASYMMETRIC_PWM2
-/**
-@endcond
-  */
-
-/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
-  * @{
-  */
-#define LL_TIM_OCMODE_FROZEN                   0x00000000U                                              /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
-#define LL_TIM_OCMODE_ACTIVE                   TIM_CCMR1_OC1M_0                                         /*!<OCyREF is forced high on compare match*/
-#define LL_TIM_OCMODE_INACTIVE                 TIM_CCMR1_OC1M_1                                         /*!<OCyREF is forced low on compare match*/
-#define LL_TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)                    /*!<OCyREF toggles on compare match*/
-#define LL_TIM_OCMODE_FORCED_INACTIVE          TIM_CCMR1_OC1M_2                                         /*!<OCyREF is forced low*/
-#define LL_TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)                    /*!<OCyREF is forced high*/
-#define LL_TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)                    /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive.  In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
-#define LL_TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active.  In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
-#define LL_TIM_OCMODE_RETRIG_OPM1              TIM_CCMR1_OC1M_3                                         /*!<Retrigerrable OPM mode 1*/
-#define LL_TIM_OCMODE_RETRIG_OPM2              (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)                    /*!<Retrigerrable OPM mode 2*/
-#define LL_TIM_OCMODE_COMBINED_PWM1            (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)                    /*!<Combined PWM mode 1*/
-#define LL_TIM_OCMODE_COMBINED_PWM2            (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/
-#define LL_TIM_OCMODE_ASYMMETRIC_PWM1          (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
-#define LL_TIM_OCMODE_ASYMMETRIC_PWM2          (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)                      /*!<Asymmetric PWM mode 2*/
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
-  * @{
-  */
-#define LL_TIM_OCPOLARITY_HIGH                 0x00000000U                 /*!< OCxactive high*/
-#define LL_TIM_OCPOLARITY_LOW                  TIM_CCER_CC1P               /*!< OCxactive low*/
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
-  * @{
-  */
-#define LL_TIM_OCIDLESTATE_LOW                 0x00000000U             /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
-#define LL_TIM_OCIDLESTATE_HIGH                TIM_CR2_OIS1            /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
-  * @{
-  */
-#define LL_TIM_GROUPCH5_NONE                   0x00000000U           /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
-#define LL_TIM_GROUPCH5_OC1REFC                TIM_CCR5_GC5C1        /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
-#define LL_TIM_GROUPCH5_OC2REFC                TIM_CCR5_GC5C2        /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
-#define LL_TIM_GROUPCH5_OC3REFC                TIM_CCR5_GC5C3        /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
-  * @{
-  */
-#define LL_TIM_ACTIVEINPUT_DIRECTTI            (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
-#define LL_TIM_ACTIVEINPUT_INDIRECTTI          (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
-#define LL_TIM_ACTIVEINPUT_TRC                 (TIM_CCMR1_CC1S << 16U)   /*!< ICx is mapped on TRC */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
-  * @{
-  */
-#define LL_TIM_ICPSC_DIV1                      0x00000000U                    /*!< No prescaler, capture is done each time an edge is detected on the capture input */
-#define LL_TIM_ICPSC_DIV2                      (TIM_CCMR1_IC1PSC_0 << 16U)    /*!< Capture is done once every 2 events */
-#define LL_TIM_ICPSC_DIV4                      (TIM_CCMR1_IC1PSC_1 << 16U)    /*!< Capture is done once every 4 events */
-#define LL_TIM_ICPSC_DIV8                      (TIM_CCMR1_IC1PSC << 16U)      /*!< Capture is done once every 8 events */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
-  * @{
-  */
-#define LL_TIM_IC_FILTER_FDIV1                 0x00000000U                                                        /*!< No filter, sampling is done at fDTS */
-#define LL_TIM_IC_FILTER_FDIV1_N2              (TIM_CCMR1_IC1F_0 << 16U)                                          /*!< fSAMPLING=fCK_INT, N=2 */
-#define LL_TIM_IC_FILTER_FDIV1_N4              (TIM_CCMR1_IC1F_1 << 16U)                                          /*!< fSAMPLING=fCK_INT, N=4 */
-#define LL_TIM_IC_FILTER_FDIV1_N8              ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fCK_INT, N=8 */
-#define LL_TIM_IC_FILTER_FDIV2_N6              (TIM_CCMR1_IC1F_2 << 16U)                                          /*!< fSAMPLING=fDTS/2, N=6 */
-#define LL_TIM_IC_FILTER_FDIV2_N8              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fDTS/2, N=8 */
-#define LL_TIM_IC_FILTER_FDIV4_N6              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)                     /*!< fSAMPLING=fDTS/4, N=6 */
-#define LL_TIM_IC_FILTER_FDIV4_N8              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/4, N=8 */
-#define LL_TIM_IC_FILTER_FDIV8_N6              (TIM_CCMR1_IC1F_3 << 16U)                                          /*!< fSAMPLING=fDTS/8, N=6 */
-#define LL_TIM_IC_FILTER_FDIV8_N8              ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fDTS/8, N=8 */
-#define LL_TIM_IC_FILTER_FDIV16_N5             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U)                     /*!< fSAMPLING=fDTS/16, N=5 */
-#define LL_TIM_IC_FILTER_FDIV16_N6             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/16, N=6 */
-#define LL_TIM_IC_FILTER_FDIV16_N8             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U)                     /*!< fSAMPLING=fDTS/16, N=8 */
-#define LL_TIM_IC_FILTER_FDIV32_N5             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/32, N=5 */
-#define LL_TIM_IC_FILTER_FDIV32_N6             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)  /*!< fSAMPLING=fDTS/32, N=6 */
-#define LL_TIM_IC_FILTER_FDIV32_N8             (TIM_CCMR1_IC1F << 16U)                                            /*!< fSAMPLING=fDTS/32, N=8 */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
-  * @{
-  */
-#define LL_TIM_IC_POLARITY_RISING              0x00000000U                      /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
-#define LL_TIM_IC_POLARITY_FALLING             TIM_CCER_CC1P                    /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
-#define LL_TIM_IC_POLARITY_BOTHEDGE            (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
-  * @{
-  */
-#define LL_TIM_CLOCKSOURCE_INTERNAL            0x00000000U                                          /*!< The timer is clocked by the internal clock provided from the RCC */
-#define LL_TIM_CLOCKSOURCE_EXT_MODE1           (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)   /*!< Counter counts at each rising or falling edge on a selected input*/
-#define LL_TIM_CLOCKSOURCE_EXT_MODE2           TIM_SMCR_ECE                                         /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
-  * @{
-  */
-#define LL_TIM_ENCODERMODE_X2_TI1                     TIM_SMCR_SMS_0                                                     /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
-#define LL_TIM_ENCODERMODE_X2_TI2                     TIM_SMCR_SMS_1                                                     /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
-#define LL_TIM_ENCODERMODE_X4_TI12                   (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)                                   /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_TRGO Trigger Output
-  * @{
-  */
-#define LL_TIM_TRGO_RESET                      0x00000000U                                     /*!< UG bit from the TIMx_EGR register is used as trigger output */
-#define LL_TIM_TRGO_ENABLE                     TIM_CR2_MMS_0                                   /*!< Counter Enable signal (CNT_EN) is used as trigger output */
-#define LL_TIM_TRGO_UPDATE                     TIM_CR2_MMS_1                                   /*!< Update event is used as trigger output */
-#define LL_TIM_TRGO_CC1IF                      (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)                 /*!< CC1 capture or a compare match is used as trigger output */
-#define LL_TIM_TRGO_OC1REF                     TIM_CR2_MMS_2                                   /*!< OC1REF signal is used as trigger output */
-#define LL_TIM_TRGO_OC2REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)                 /*!< OC2REF signal is used as trigger output */
-#define LL_TIM_TRGO_OC3REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)                 /*!< OC3REF signal is used as trigger output */
-#define LL_TIM_TRGO_OC4REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
-  * @{
-  */
-#define LL_TIM_TRGO2_RESET                     0x00000000U                                                         /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */
-#define LL_TIM_TRGO2_ENABLE                    TIM_CR2_MMS2_0                                                      /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */
-#define LL_TIM_TRGO2_UPDATE                    TIM_CR2_MMS2_1                                                      /*!< Update event is used as trigger output 2 */
-#define LL_TIM_TRGO2_CC1F                      (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                                   /*!< CC1 capture or a compare match is used as trigger output 2 */
-#define LL_TIM_TRGO2_OC1                       TIM_CR2_MMS2_2                                                      /*!< OC1REF signal is used as trigger output 2 */
-#define LL_TIM_TRGO2_OC2                       (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                                   /*!< OC2REF signal is used as trigger output 2 */
-#define LL_TIM_TRGO2_OC3                       (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)                                   /*!< OC3REF signal is used as trigger output 2 */
-#define LL_TIM_TRGO2_OC4                       (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC4REF signal is used as trigger output 2 */
-#define LL_TIM_TRGO2_OC5                       TIM_CR2_MMS2_3                                                      /*!< OC5REF signal is used as trigger output 2 */
-#define LL_TIM_TRGO2_OC6                       (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)                                   /*!< OC6REF signal is used as trigger output 2 */
-#define LL_TIM_TRGO2_OC4_RISINGFALLING         (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)                                   /*!< OC4REF rising or falling edges are used as trigger output 2 */
-#define LL_TIM_TRGO2_OC6_RISINGFALLING         (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC6REF rising or falling edges are used as trigger output 2 */
-#define LL_TIM_TRGO2_OC4_RISING_OC6_RISING     (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)                                   /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */
-#define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                  /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */
-#define LL_TIM_TRGO2_OC5_RISING_OC6_RISING     (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)                   /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */
-#define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
-  * @{
-  */
-#define LL_TIM_SLAVEMODE_DISABLED              0x00000000U                         /*!< Slave mode disabled */
-#define LL_TIM_SLAVEMODE_RESET                 TIM_SMCR_SMS_2                      /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
-#define LL_TIM_SLAVEMODE_GATED                 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)   /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
-#define LL_TIM_SLAVEMODE_TRIGGER               (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)   /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
-#define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3                      /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI)  reinitializes the counter, generates an update of the registers and starts the counter */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_TS Trigger Selection
-  * @{
-  */
-#define LL_TIM_TS_ITR0                         0x00000000U                                                     /*!< Internal Trigger 0 (ITR0) is used as trigger input */
-#define LL_TIM_TS_ITR1                         TIM_SMCR_TS_0                                                   /*!< Internal Trigger 1 (ITR1) is used as trigger input */
-#define LL_TIM_TS_ITR2                         TIM_SMCR_TS_1                                                   /*!< Internal Trigger 2 (ITR2) is used as trigger input */
-#define LL_TIM_TS_ITR3                         (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)                                 /*!< Internal Trigger 3 (ITR3) is used as trigger input */
-#define LL_TIM_TS_ITR4                         (TIM_SMCR_TS_3)                                                 /*!< Internal Trigger 4 (ITR4) is used as trigger input */
-#define LL_TIM_TS_ITR5                         (TIM_SMCR_TS_0 | TIM_SMCR_TS_3)                                 /*!< Internal Trigger 5 (ITR5) is used as trigger input */
-#define LL_TIM_TS_ITR6                         (TIM_SMCR_TS_1 | TIM_SMCR_TS_3)                                 /*!< Internal Trigger 6 (ITR6) is used as trigger input */
-#define LL_TIM_TS_ITR7                         (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3)                 /*!< Internal Trigger 7 (ITR7) is used as trigger input */
-#define LL_TIM_TS_ITR8                         (TIM_SMCR_TS_2 | TIM_SMCR_TS_3)                                 /*!< Internal Trigger 8 (ITR8) is used as trigger input */
-#define LL_TIM_TS_ITR9                         (TIM_SMCR_TS_0 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)                 /*!< Internal Trigger 9 (ITR9) is used as trigger input */
-#define LL_TIM_TS_ITR10                        (TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)                 /*!< Internal Trigger 10 (ITR10) is used as trigger input */
-#define LL_TIM_TS_ITR11                        (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 11 (ITR11) is used as trigger input */
-#define LL_TIM_TS_ITR12                        (TIM_SMCR_TS_4)                                                 /*!< Internal Trigger 12 (ITR12) is used as trigger input */
-#define LL_TIM_TS_ITR13                        (TIM_SMCR_TS_0 | TIM_SMCR_TS_4)                                 /*!< Internal Trigger 13 (ITR13) is used as trigger input */
-#define LL_TIM_TS_TI1F_ED                      TIM_SMCR_TS_2                                                   /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
-#define LL_TIM_TS_TI1FP1                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_0)                                 /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
-#define LL_TIM_TS_TI2FP2                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_1)                                 /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
-#define LL_TIM_TS_ETRF                         (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0)                 /*!< Filtered external Trigger (ETRF) is used as trigger input */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
-  * @{
-  */
-#define LL_TIM_ETR_POLARITY_NONINVERTED        0x00000000U             /*!< ETR is non-inverted, active at high level or rising edge */
-#define LL_TIM_ETR_POLARITY_INVERTED           TIM_SMCR_ETP            /*!< ETR is inverted, active at low level or falling edge */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
-  * @{
-  */
-#define LL_TIM_ETR_PRESCALER_DIV1              0x00000000U             /*!< ETR prescaler OFF */
-#define LL_TIM_ETR_PRESCALER_DIV2              TIM_SMCR_ETPS_0         /*!< ETR frequency is divided by 2 */
-#define LL_TIM_ETR_PRESCALER_DIV4              TIM_SMCR_ETPS_1         /*!< ETR frequency is divided by 4 */
-#define LL_TIM_ETR_PRESCALER_DIV8              TIM_SMCR_ETPS           /*!< ETR frequency is divided by 8 */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
-  * @{
-  */
-#define LL_TIM_ETR_FILTER_FDIV1                0x00000000U                                          /*!< No filter, sampling is done at fDTS */
-#define LL_TIM_ETR_FILTER_FDIV1_N2             TIM_SMCR_ETF_0                                       /*!< fSAMPLING=fCK_INT, N=2 */
-#define LL_TIM_ETR_FILTER_FDIV1_N4             TIM_SMCR_ETF_1                                       /*!< fSAMPLING=fCK_INT, N=4 */
-#define LL_TIM_ETR_FILTER_FDIV1_N8             (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fCK_INT, N=8 */
-#define LL_TIM_ETR_FILTER_FDIV2_N6             TIM_SMCR_ETF_2                                       /*!< fSAMPLING=fDTS/2, N=6 */
-#define LL_TIM_ETR_FILTER_FDIV2_N8             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fDTS/2, N=8 */
-#define LL_TIM_ETR_FILTER_FDIV4_N6             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)                    /*!< fSAMPLING=fDTS/4, N=6 */
-#define LL_TIM_ETR_FILTER_FDIV4_N8             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/4, N=8 */
-#define LL_TIM_ETR_FILTER_FDIV8_N6             TIM_SMCR_ETF_3                                       /*!< fSAMPLING=fDTS/8, N=6 */
-#define LL_TIM_ETR_FILTER_FDIV8_N8             (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fDTS/16, N=8 */
-#define LL_TIM_ETR_FILTER_FDIV16_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1)                    /*!< fSAMPLING=fDTS/16, N=5 */
-#define LL_TIM_ETR_FILTER_FDIV16_N6            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/16, N=6 */
-#define LL_TIM_ETR_FILTER_FDIV16_N8            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2)                    /*!< fSAMPLING=fDTS/16, N=8 */
-#define LL_TIM_ETR_FILTER_FDIV32_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/32, N=5 */
-#define LL_TIM_ETR_FILTER_FDIV32_N6            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)   /*!< fSAMPLING=fDTS/32, N=6 */
-#define LL_TIM_ETR_FILTER_FDIV32_N8            TIM_SMCR_ETF                                         /*!< fSAMPLING=fDTS/32, N=8 */
-/**
-  * @}
-  */
-
-#define LL_TIM_TIM1_ETRSOURCE_GPIO        0x00000000U                                                 /*!< TIM1_ETR is connected to GPIO */
-#define LL_TIM_TIM1_ETRSOURCE_COMP1       TIM1_AF1_ETRSEL_0                                           /*!< TIM1_ETR is connected to COMP1 OUT */
-#define LL_TIM_TIM1_ETRSOURCE_COMP2       TIM1_AF1_ETRSEL_1                                           /*!< TIM1_ETR is connected to COMP2 OUT */
-#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1   (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)                     /*!< TIM1_ETR is connected to ADC1 AWD1 */
-#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2   (TIM1_AF1_ETRSEL_2)                                         /*!< TIM1_ETR is connected to ADC1 AWD2 */
-#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)                     /*!< TIM1_ETR is connected to ADC1 AWD3 */
-#define LL_TIM_TIM1_ETRSOURCE_ADC3_AWD1   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1)                     /*!< TIM1_ETR is connected to ADC3 AWD1 */
-#define LL_TIM_TIM1_ETRSOURCE_ADC3_AWD2   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC3 AWD2 */
-#define LL_TIM_TIM1_ETRSOURCE_ADC3_AWD3   TIM1_AF1_ETRSEL_3                                           /*!< TIM1_ETR is connected to ADC3 AWD3 */
-
-#define LL_TIM_TIM8_ETRSOURCE_GPIO        0x00000000U                                                 /*!< TIM8_ETR is connected to GPIO */
-#define LL_TIM_TIM8_ETRSOURCE_COMP1       TIM8_AF1_ETRSEL_0                                           /*!< TIM8_ETR is connected to COMP1 OUT */
-#define LL_TIM_TIM8_ETRSOURCE_COMP2       TIM8_AF1_ETRSEL_1                                           /*!< TIM8_ETR is connected to COMP2 OUT */
-#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1   (TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0)                     /*!< TIM8_ETR is connected to ADC2 AWD1 */
-#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2   (TIM8_AF1_ETRSEL_2)                                         /*!< TIM8_ETR is connected to ADC2 AWD2 */
-#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0)                     /*!< TIM8_ETR is connected to ADC2 AWD3 */
-#define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD1   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1)                     /*!< TIM8_ETR is connected to ADC3 AWD1 */
-#define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD2   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to ADC3 AWD2 */
-#define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD3   TIM8_AF1_ETRSEL_3                                           /*!< TIM8_ETR is connected to ADC3 AWD3 */
-
-#define LL_TIM_TIM2_ETRSOURCE_GPIO        0x00000000U                                                 /*!< TIM2_ETR is connected to GPIO */
-#define LL_TIM_TIM2_ETRSOURCE_COMP1       (TIM2_AF1_ETRSEL_0)                                         /*!< TIM2_ETR is connected to COMP1 OUT */
-#define LL_TIM_TIM2_ETRSOURCE_COMP2       (TIM2_AF1_ETRSEL_1)                                         /*!< TIM2_ETR is connected to COMP2 OUT */
-#define LL_TIM_TIM2_ETRSOURCE_RCC_LSE     (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0)                     /*!< TIM2_ETR is connected to RCC LSE */
-#define LL_TIM_TIM2_ETRSOURCE_SAI1_FSA    TIM2_AF1_ETRSEL_2                                           /*!< TIM2_ETR is connected to SAI1 FS_A */
-#define LL_TIM_TIM2_ETRSOURCE_SAI1_FSB    (TIM2_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0)                     /*!< TIM2_ETR is connected to SAI1 FS_B */
-
-#define LL_TIM_TIM3_ETRSOURCE_GPIO        0x00000000U                                                 /*!< TIM3_ETR is connected to GPIO */
-#define LL_TIM_TIM3_ETRSOURCE_COMP1       TIM3_AF1_ETRSEL_0                                           /*!< TIM3_ETR is connected to COMP1 OUT */
-
-#define LL_TIM_TIM5_ETRSOURCE_GPIO        0x00000000U                                                 /*!< TIM5_ETR is connected to GPIO */
-#define LL_TIM_TIM5_ETRSOURCE_SAI2_FSA    TIM5_AF1_ETRSEL_0                                           /*!< TIM5_ETR is connected to SAI2 FS_A */
-#define LL_TIM_TIM5_ETRSOURCE_SAI2_FSB    TIM5_AF1_ETRSEL_1                                           /*!< TIM5_ETR is connected to SAI2 FS_B */
-#define LL_TIM_TIM5_ETRSOURCE_SAI4_FSA    TIM5_AF1_ETRSEL_0                                           /*!< TIM5_ETR is connected to SAI4 FS_A */
-#define LL_TIM_TIM5_ETRSOURCE_SAI4_FSB    TIM5_AF1_ETRSEL_1                                           /*!< TIM5_ETR is connected to SAI4 FS_B */
-
-#define LL_TIM_TIM23_ETRSOURCE_GPIO       0x00000000U                                                 /*!< TIM23_ETR is connected to GPIO */
-#define LL_TIM_TIM23_ETRSOURCE_COMP1      (TIM2_AF1_ETRSEL_0)                                         /*!< TIM23_ETR is connected to COMP1 OUT */
-#define LL_TIM_TIM23_ETRSOURCE_COMP2      (TIM2_AF1_ETRSEL_1)                                         /*!< TIM23_ETR is connected to COMP2 OUT */
-
-#define LL_TIM_TIM24_ETRSOURCE_GPIO        0x00000000U                                                /*!< TIM24_ETR is connected to GPIO */
-#define LL_TIM_TIM24_ETRSOURCE_SAI4_FSA    TIM5_AF1_ETRSEL_0                                          /*!< TIM24_ETR is connected to SAI4 FS_A */
-#define LL_TIM_TIM24_ETRSOURCE_SAI4_FSB    TIM5_AF1_ETRSEL_1                                          /*!< TIM24_ETR is connected to SAI4 FS_B */
-#define LL_TIM_TIM24_ETRSOURCE_SAI1_FSA    (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0)                    /*!< TIM24_ETR is connected to SAI1 FS_A */
-#define LL_TIM_TIM24_ETRSOURCE_SAI1_FSB    TIM2_AF1_ETRSEL_2                                          /*!< TIM24_ETR is connected to SAI1 FS_B */
-
-/** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
-  * @{
-  */
-#define LL_TIM_BREAK_POLARITY_LOW              0x00000000U               /*!< Break input BRK is active low */
-#define LL_TIM_BREAK_POLARITY_HIGH             TIM_BDTR_BKP              /*!< Break input BRK is active high */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_BREAK_FILTER break filter
-  * @{
-  */
-#define LL_TIM_BREAK_FILTER_FDIV1              0x00000000U   /*!< No filter, BRK acts asynchronously */
-#define LL_TIM_BREAK_FILTER_FDIV1_N2           0x00010000U   /*!< fSAMPLING=fCK_INT, N=2 */
-#define LL_TIM_BREAK_FILTER_FDIV1_N4           0x00020000U   /*!< fSAMPLING=fCK_INT, N=4 */
-#define LL_TIM_BREAK_FILTER_FDIV1_N8           0x00030000U   /*!< fSAMPLING=fCK_INT, N=8 */
-#define LL_TIM_BREAK_FILTER_FDIV2_N6           0x00040000U   /*!< fSAMPLING=fDTS/2, N=6 */
-#define LL_TIM_BREAK_FILTER_FDIV2_N8           0x00050000U   /*!< fSAMPLING=fDTS/2, N=8 */
-#define LL_TIM_BREAK_FILTER_FDIV4_N6           0x00060000U   /*!< fSAMPLING=fDTS/4, N=6 */
-#define LL_TIM_BREAK_FILTER_FDIV4_N8           0x00070000U   /*!< fSAMPLING=fDTS/4, N=8 */
-#define LL_TIM_BREAK_FILTER_FDIV8_N6           0x00080000U   /*!< fSAMPLING=fDTS/8, N=6 */
-#define LL_TIM_BREAK_FILTER_FDIV8_N8           0x00090000U   /*!< fSAMPLING=fDTS/8, N=8 */
-#define LL_TIM_BREAK_FILTER_FDIV16_N5          0x000A0000U   /*!< fSAMPLING=fDTS/16, N=5 */
-#define LL_TIM_BREAK_FILTER_FDIV16_N6          0x000B0000U   /*!< fSAMPLING=fDTS/16, N=6 */
-#define LL_TIM_BREAK_FILTER_FDIV16_N8          0x000C0000U   /*!< fSAMPLING=fDTS/16, N=8 */
-#define LL_TIM_BREAK_FILTER_FDIV32_N5          0x000D0000U   /*!< fSAMPLING=fDTS/32, N=5 */
-#define LL_TIM_BREAK_FILTER_FDIV32_N6          0x000E0000U   /*!< fSAMPLING=fDTS/32, N=6 */
-#define LL_TIM_BREAK_FILTER_FDIV32_N8          0x000F0000U   /*!< fSAMPLING=fDTS/32, N=8 */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
-  * @{
-  */
-#define LL_TIM_BREAK2_POLARITY_LOW             0x00000000U             /*!< Break input BRK2 is active low */
-#define LL_TIM_BREAK2_POLARITY_HIGH            TIM_BDTR_BK2P           /*!< Break input BRK2 is active high */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
-  * @{
-  */
-#define LL_TIM_BREAK2_FILTER_FDIV1             0x00000000U   /*!< No filter, BRK acts asynchronously */
-#define LL_TIM_BREAK2_FILTER_FDIV1_N2          0x00100000U   /*!< fSAMPLING=fCK_INT, N=2 */
-#define LL_TIM_BREAK2_FILTER_FDIV1_N4          0x00200000U   /*!< fSAMPLING=fCK_INT, N=4 */
-#define LL_TIM_BREAK2_FILTER_FDIV1_N8          0x00300000U   /*!< fSAMPLING=fCK_INT, N=8 */
-#define LL_TIM_BREAK2_FILTER_FDIV2_N6          0x00400000U   /*!< fSAMPLING=fDTS/2, N=6 */
-#define LL_TIM_BREAK2_FILTER_FDIV2_N8          0x00500000U   /*!< fSAMPLING=fDTS/2, N=8 */
-#define LL_TIM_BREAK2_FILTER_FDIV4_N6          0x00600000U   /*!< fSAMPLING=fDTS/4, N=6 */
-#define LL_TIM_BREAK2_FILTER_FDIV4_N8          0x00700000U   /*!< fSAMPLING=fDTS/4, N=8 */
-#define LL_TIM_BREAK2_FILTER_FDIV8_N6          0x00800000U   /*!< fSAMPLING=fDTS/8, N=6 */
-#define LL_TIM_BREAK2_FILTER_FDIV8_N8          0x00900000U   /*!< fSAMPLING=fDTS/8, N=8 */
-#define LL_TIM_BREAK2_FILTER_FDIV16_N5         0x00A00000U   /*!< fSAMPLING=fDTS/16, N=5 */
-#define LL_TIM_BREAK2_FILTER_FDIV16_N6         0x00B00000U   /*!< fSAMPLING=fDTS/16, N=6 */
-#define LL_TIM_BREAK2_FILTER_FDIV16_N8         0x00C00000U   /*!< fSAMPLING=fDTS/16, N=8 */
-#define LL_TIM_BREAK2_FILTER_FDIV32_N5         0x00D00000U   /*!< fSAMPLING=fDTS/32, N=5 */
-#define LL_TIM_BREAK2_FILTER_FDIV32_N6         0x00E00000U   /*!< fSAMPLING=fDTS/32, N=6 */
-#define LL_TIM_BREAK2_FILTER_FDIV32_N8         0x00F00000U   /*!< fSAMPLING=fDTS/32, N=8 */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_OSSI OSSI
-  * @{
-  */
-#define LL_TIM_OSSI_DISABLE                    0x00000000U             /*!< When inactive, OCx/OCxN outputs are disabled */
-#define LL_TIM_OSSI_ENABLE                     TIM_BDTR_OSSI           /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_OSSR OSSR
-  * @{
-  */
-#define LL_TIM_OSSR_DISABLE                    0x00000000U             /*!< When inactive, OCx/OCxN outputs are disabled */
-#define LL_TIM_OSSR_ENABLE                     TIM_BDTR_OSSR           /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
-/**
-  * @}
-  */
-
-#if   defined(TIM_BREAK_INPUT_SUPPORT)
-/** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT
-  * @{
-  */
-#define LL_TIM_BREAK_INPUT_BKIN                0x00000000U  /*!< TIMx_BKIN input */
-#define LL_TIM_BREAK_INPUT_BKIN2               0x00000004U  /*!< TIMx_BKIN2 input */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE
-  * @{
-  */
-#define LL_TIM_BKIN_SOURCE_BKIN                TIM1_AF1_BKINE      /*!< BKIN input from AF controller */
-#define LL_TIM_BKIN_SOURCE_BKCOMP1             TIM1_AF1_BKCMP1E    /*!< internal signal: COMP1 output */
-#define LL_TIM_BKIN_SOURCE_BKCOMP2             TIM1_AF1_BKCMP2E    /*!< internal signal: COMP2 output */
-#define LL_TIM_BKIN_SOURCE_DF1BK               TIM1_AF1_BKDF1BK0E  /*!< internal signal: DFSDM1 break output */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY
-  * @{
-  */
-#define LL_TIM_BKIN_POLARITY_LOW               TIM1_AF1_BKINP           /*!< BRK BKIN input is active low */
-#define LL_TIM_BKIN_POLARITY_HIGH              0x00000000U              /*!< BRK BKIN input is active high */
-/**
-  * @}
-  */
-#endif /* TIM_BREAK_INPUT_SUPPORT */
-
-#if defined(TIM_BDTR_BKBID)
-/** @defgroup TIM_LL_EC_BREAK_AFMODE BREAK AF MODE
-  * @{
-  */
-#define LL_TIM_BREAK_AFMODE_INPUT              0x00000000U              /*!< Break input BRK in input mode */
-#define LL_TIM_BREAK_AFMODE_BIDIRECTIONAL      TIM_BDTR_BKBID           /*!< Break input BRK in bidirectional mode */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_BREAK2_AFMODE BREAK2 AF MODE
-  * @{
-  */
-#define LL_TIM_BREAK2_AFMODE_INPUT             0x00000000U             /*!< Break2 input BRK2 in input mode */
-#define LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL     TIM_BDTR_BK2BID         /*!< Break2 input BRK2 in bidirectional mode */
-/**
-  * @}
-  */
-
-/** Legacy definitions for compatibility purpose
-@cond 0
-  */
-#define LL_TIM_ReArmBRK(_PARAM_)
-#define LL_TIM_ReArmBRK2(_PARAM_)
-/**
-@endcond
-  */
-
-#endif /*TIM_BDTR_BKBID */
-/** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
-  * @{
-  */
-#define LL_TIM_DMABURST_BASEADDR_CR1           0x00000000U                                                      /*!< TIMx_CR1 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CR2           TIM_DCR_DBA_0                                                    /*!< TIMx_CR2 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_SMCR          TIM_DCR_DBA_1                                                    /*!< TIMx_SMCR register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_DIER          (TIM_DCR_DBA_1 |  TIM_DCR_DBA_0)                                 /*!< TIMx_DIER register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_SR            TIM_DCR_DBA_2                                                    /*!< TIMx_SR register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_EGR           (TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                                  /*!< TIMx_EGR register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCMR1         (TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                                  /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCMR2         (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)                  /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCER          TIM_DCR_DBA_3                                                    /*!< TIMx_CCER register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CNT           (TIM_DCR_DBA_3 | TIM_DCR_DBA_0)                                  /*!< TIMx_CNT register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_PSC           (TIM_DCR_DBA_3 | TIM_DCR_DBA_1)                                  /*!< TIMx_PSC register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_ARR           (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)                  /*!< TIMx_ARR register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_RCR           (TIM_DCR_DBA_3 | TIM_DCR_DBA_2)                                  /*!< TIMx_RCR register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCR1          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                  /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCR2          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                  /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCR3          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)  /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCR4          TIM_DCR_DBA_4                                                    /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_BDTR          (TIM_DCR_DBA_4 | TIM_DCR_DBA_0)                                  /*!< TIMx_BDTR register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCMR3         (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                  /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCR5          (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                  /*!< TIMx_CCR5 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCR6          (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)  /*!< TIMx_CCR6 register is the DMA base address for DMA burst */
-#if defined(TIM1_AF1_BKINE)&&defined(TIM1_AF2_BKINE)
-#define LL_TIM_DMABURST_BASEADDR_AF1           (TIM_DCR_DBA_4 | TIM_DCR_DBA_3)                                  /*!< TIMx_AF1 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_AF2           (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0)                  /*!< TIMx_AF2 register is the DMA base address for DMA burst */
-#endif /* TIM1_AF1_BKINE && TIM1_AF2_BKINE */
-#define LL_TIM_DMABURST_BASEADDR_TISEL         (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_1)                  /*!< TIMx_TISEL register is the DMA base address for DMA burst */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
-  * @{
-  */
-#define LL_TIM_DMABURST_LENGTH_1TRANSFER       0x00000000U                                                     /*!< Transfer is done to 1 register starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_2TRANSFERS      TIM_DCR_DBL_0                                                   /*!< Transfer is done to 2 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_3TRANSFERS      TIM_DCR_DBL_1                                                   /*!< Transfer is done to 3 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_4TRANSFERS      (TIM_DCR_DBL_1 |  TIM_DCR_DBL_0)                                /*!< Transfer is done to 4 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_5TRANSFERS      TIM_DCR_DBL_2                                                   /*!< Transfer is done to 5 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_6TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_0)                                 /*!< Transfer is done to 6 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_7TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_1)                                 /*!< Transfer is done to 7 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_8TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 1 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_9TRANSFERS      TIM_DCR_DBL_3                                                   /*!< Transfer is done to 9 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_10TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_0)                                 /*!< Transfer is done to 10 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_11TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_1)                                 /*!< Transfer is done to 11 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_12TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 12 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_13TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2)                                 /*!< Transfer is done to 13 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_14TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 14 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_15TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1)                 /*!< Transfer is done to 15 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_16TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_17TRANSFERS     TIM_DCR_DBL_4                                                   /*!< Transfer is done to 17 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_18TRANSFERS     (TIM_DCR_DBL_4 |  TIM_DCR_DBL_0)                                /*!< Transfer is done to 18 registers starting from the DMA burst base address */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_TIM1_TI1_RMP  TIM1 Timer Input Ch1 Remap
-  * @{
-  */
-#define LL_TIM_TIM1_TI1_RMP_GPIO                          0x00000000U                               /*!< TIM1 input 1 is connected to GPIO */
-#define LL_TIM_TIM1_TI1_RMP_COMP1                         TIM_TISEL_TI1SEL_0                        /*!< TIM1 input 1 is connected to COMP1 OUT */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_TIM8_TI1_RMP  TIM8 Timer Input Ch1 Remap
-  * @{
-  */
-#define LL_TIM_TIM8_TI1_RMP_GPIO                          0x00000000U                               /*!< TIM8 input 1 is connected to GPIO */
-#define LL_TIM_TIM8_TI1_RMP_COMP2                         TIM_TISEL_TI1SEL_0                        /*!< TIM8 input 1 is connected to COMP2 OUT */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_TIM2_TI4_RMP  TIM2 Timer Input Ch4 Remap
-  * @{
-  */
-#define LL_TIM_TIM2_TI4_RMP_GPIO                          0x00000000U                               /*!< TIM2 input 4 is connected to GPIO */
-#define LL_TIM_TIM2_TI4_RMP_COMP1                         TIM_TISEL_TI4SEL_0                        /*!< TIM2 input 4 is connected to COMP1 OUT */
-#define LL_TIM_TIM2_TI4_RMP_COMP2                         TIM_TISEL_TI4SEL_1                        /*!< TIM2 input 4 is connected to COMP2 OUT */
-#define LL_TIM_TIM2_TI4_RMP_COMP1_COMP2                   (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /*!< TIM2 input 4 is connected to COMP2 OUT OR COMP2 OUT */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_TIM3_TI1_RMP  TIM3 Timer Input Ch1 Remap
-  * @{
-  */
-#define LL_TIM_TIM3_TI1_RMP_GPIO                          0x00000000U                               /*!< TIM3 input 1 is connected to GPIO */
-#define LL_TIM_TIM3_TI1_RMP_COMP1                         TIM_TISEL_TI1SEL_0                        /*!< TIM3 input 1 is connected to COMP1 OUT */
-#define LL_TIM_TIM3_TI1_RMP_COMP2                         TIM_TISEL_TI1SEL_1                        /*!< TIM3 input 1 is connected to COMP2 OUT */
-#define LL_TIM_TIM3_TI1_RMP_COMP1_COMP2                   (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM3 input 1 is connected to COMP1 OUT or COMP2 OUT */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_TIM5_TI1_RMP  TIM5 Timer Input Ch1 Remap
-  * @{
-  */
-#define LL_TIM_TIM5_TI1_RMP_GPIO                          0x00000000U                               /*!< TIM5 input 1 is connected to GPIO */
-#define LL_TIM_TIM5_TI1_RMP_CAN_TMP                       TIM_TISEL_TI1SEL_0                        /*!< TIM5 input 1 is connected to CAN TMP */
-#define LL_TIM_TIM5_TI1_RMP_CAN_RTP                       TIM_TISEL_TI1SEL_1                        /*!< TIM5 input 1 is connected to CAN RTP */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_TIM12_TI1_RMP  TIM12 Timer Input Ch1 Remap
-  * @{
-  */
-#define LL_TIM_TIM12_TI1_RMP_GPIO                         0x00000000U                               /*!< TIM12 input 1 is connected to GPIO */
-#define LL_TIM_TIM12_TI1_RMP_SPDIF_FS                     TIM_TISEL_TI1SEL_0                        /*!< TIM12 input 1 is connected to SPDIF FS */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_TIM15_TI1_RMP  TIM15 Timer Input Ch1 Remap
-  * @{
-  */
-#define LL_TIM_TIM15_TI1_RMP_GPIO                         0x00000000U                               /*!< TIM15 input 1 is connected to GPIO */
-#define LL_TIM_TIM15_TI1_RMP_TIM2_CH1                     TIM_TISEL_TI1SEL_0                        /*!< TIM15 input 1 is connected to TIM2 CH1 */
-#define LL_TIM_TIM15_TI1_RMP_TIM3_CH1                     TIM_TISEL_TI1SEL_1                        /*!< TIM15 input 1 is connected to TIM3 CH1 */
-#define LL_TIM_TIM15_TI1_RMP_TIM4_CH1                     (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM15 input 1 is connected to TIM4 CH1 */
-#define LL_TIM_TIM15_TI1_RMP_RCC_LSE                      (TIM_TISEL_TI1SEL_2)                      /*!< TIM15 input 1 is connected to RCC LSE  */
-#define LL_TIM_TIM15_TI1_RMP_RCC_CSI                      (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM15 input 1 is connected to RCC CSI  */
-#define LL_TIM_TIM15_TI1_RMP_RCC_MCO2                     (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM15 input 1 is connected to RCC MCO2 */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_TIM15_TI2_RMP  TIM15 Timer Input Ch2 Remap
-  * @{
-  */
-#define LL_TIM_TIM15_TI2_RMP_GPIO                         0x00000000U                               /*!< TIM15 input 2 is connected to GPIO */
-#define LL_TIM_TIM15_TI2_RMP_TIM2_CH2                     (TIM_TISEL_TI2SEL_0)                      /*!< TIM15 input 2 is connected to TIM2 CH2 */
-#define LL_TIM_TIM15_TI2_RMP_TIM3_CH2                     (TIM_TISEL_TI2SEL_1)                      /*!< TIM15 input 2 is connected to TIM3 CH2 */
-#define LL_TIM_TIM15_TI2_RMP_TIM4_CH2                     (TIM_TISEL_TI2SEL_0 | TIM_TISEL_TI2SEL_1) /*!< TIM15 input 2 is connected to TIM4 CH2 */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_TIM16_TI1_RMP  TIM16 Timer Input Ch1 Remap
-  * @{
-  */
-#define LL_TIM_TIM16_TI1_RMP_GPIO                         0x00000000U                               /*!< TIM16 input 1 is connected to GPIO */
-#define LL_TIM_TIM16_TI1_RMP_RCC_LSI                      TIM_TISEL_TI1SEL_0                        /*!< TIM16 input 1 is connected to RCC LSI */
-#define LL_TIM_TIM16_TI1_RMP_RCC_LSE                      TIM_TISEL_TI1SEL_1                        /*!< TIM16 input 1 is connected to RCC LSE */
-#define LL_TIM_TIM16_TI1_RMP_WKUP_IT                      (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM16 input 1 is connected to WKUP_IT */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_TIM17_TI1_RMP  TIM17 Timer Input Ch1 Remap
-  * @{
-  */
-#define LL_TIM_TIM17_TI1_RMP_GPIO                         0x00000000U                               /*!< TIM17 input 1 is connected to GPIO */
-#define LL_TIM_TIM17_TI1_RMP_SPDIF_FS                     TIM_TISEL_TI1SEL_0                        /*!< TIM17 input 1 is connected to SPDIF FS */
-#define LL_TIM_TIM17_TI1_RMP_RCC_HSE1MHZ                  TIM_TISEL_TI1SEL_1                        /*!< TIM17 input 1 is connected to RCC HSE 1Mhz */
-#define LL_TIM_TIM17_TI1_RMP_RCC_MCO1                     (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM17 input 1 is connected to RCC MCO1 */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_TIM23_TI4_RMP  TIM23 Timer Input Ch4 Remap
-  * @{
-  */
-#define LL_TIM_TIM23_TI4_RMP_GPIO                         0x00000000U                               /*!< TIM23 input 4 is connected to GPIO */
-#define LL_TIM_TIM23_TI4_RMP_COMP1                        TIM_TISEL_TI4SEL_0                        /*!< TIM23 input 4 is connected to COMP1 OUT */
-#define LL_TIM_TIM23_TI4_RMP_COMP2                        TIM_TISEL_TI4SEL_1                        /*!< TIM23 input 4 is connected to COMP2 OUT */
-#define LL_TIM_TIM23_TI4_RMP_COMP1_COMP2                  (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /*!< TIM23 input 4 is connected to COMP1 OUT or COMP2 OUT */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_TIM24_TI1_RMP  TIM24 Timer Input Ch1 Remap
-  * @{
-  */
-#define LL_TIM_TIM24_TI1_RMP_GPIO                         0x00000000U                               /*!< TIM24 input 1 is connected to GPIO */
-#define LL_TIM_TIM24_TI1_RMP_CAN_TMP                      TIM_TISEL_TI1SEL_0                        /*!< TIM24 input 1 is connected to CAN TMP  */
-#define LL_TIM_TIM24_TI1_RMP_CAN_RTP                      TIM_TISEL_TI1SEL_1                        /*!< TIM24 input 1 is connected to CAN RTP  */
-#define LL_TIM_TIM24_TI1_RMP_CAN_SOC                      (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /*!< TIM24 input 1 is connected to CAN SOC */
-/**
-  * @}
-  */
-
-#if defined(TIM_BREAK_INPUT_SUPPORT)
-/** Legacy definitions for compatibility purpose
-@cond 0
-  */
-#define LL_TIM_BKIN_SOURCE_DFBK  LL_TIM_BKIN_SOURCE_DF1BK
-/**
-@endcond
-  */
-#endif /* TIM_BREAK_INPUT_SUPPORT */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
-  * @{
-  */
-
-/** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
-  * @{
-  */
-/**
-  * @brief  Write a value in TIM register.
-  * @param  __INSTANCE__ TIM Instance
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in TIM register.
-  * @param  __INSTANCE__ TIM Instance
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
-/**
-  * @}
-  */
-
-/**
-  * @brief  HELPER macro retrieving the UIFCPY flag from the counter value.
-  * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
-  * @note  Relevant only if UIF flag remapping has been enabled  (UIF status bit is copied
-  *        to TIMx_CNT register bit 31)
-  * @param  __CNT__ Counter value
-  * @retval UIF status bit
-  */
-#define __LL_TIM_GETFLAG_UIFCPY(__CNT__)  \
-  (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
-
-/**
-  * @brief  HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
-  * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
-  * @param  __TIMCLK__ timer input clock frequency (in Hz)
-  * @param  __CKD__ This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
-  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
-  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
-  * @param  __DT__ deadtime duration (in ns)
-  * @retval DTG[0:7]
-  */
-#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__)  \
-  ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))    ?  \
-    (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__)))  & DT_DELAY_1) :      \
-    (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))  ?  \
-    (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__),   \
-                                                 (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
-    (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))  ?  \
-    (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__),  \
-                                                 (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
-    (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ?  \
-    (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__),  \
-                                                 (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
-    0U)
-
-/**
-  * @brief  HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
-  * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
-  * @param  __TIMCLK__ timer input clock frequency (in Hz)
-  * @param  __CNTCLK__ counter clock frequency (in Hz)
-  * @retval Prescaler value  (between Min_Data=0 and Max_Data=65535)
-  */
-#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__)   \
-  (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U)
-
-/**
-  * @brief  HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
-  * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
-  * @param  __TIMCLK__ timer input clock frequency (in Hz)
-  * @param  __PSC__ prescaler
-  * @param  __FREQ__ output signal frequency (in Hz)
-  * @retval  Auto-reload value  (between Min_Data=0 and Max_Data=65535)
-  */
-#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
-  ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
-
-/**
-  * @brief  HELPER macro calculating the compare value required to achieve the required timer output compare
-  *         active/inactive delay.
-  * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
-  * @param  __TIMCLK__ timer input clock frequency (in Hz)
-  * @param  __PSC__ prescaler
-  * @param  __DELAY__ timer output compare active/inactive delay (in us)
-  * @retval Compare value  (between Min_Data=0 and Max_Data=65535)
-  */
-#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__)  \
-  ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
-              / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
-
-/**
-  * @brief  HELPER macro calculating the auto-reload value to achieve the required pulse duration
-  *         (when the timer operates in one pulse mode).
-  * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
-  * @param  __TIMCLK__ timer input clock frequency (in Hz)
-  * @param  __PSC__ prescaler
-  * @param  __DELAY__ timer output compare active/inactive delay (in us)
-  * @param  __PULSE__ pulse duration (in us)
-  * @retval Auto-reload value  (between Min_Data=0 and Max_Data=65535)
-  */
-#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__)  \
-  ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
-              + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
-
-/**
-  * @brief  HELPER macro retrieving the ratio of the input capture prescaler
-  * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
-  * @param  __ICPSC__ This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_ICPSC_DIV1
-  *         @arg @ref LL_TIM_ICPSC_DIV2
-  *         @arg @ref LL_TIM_ICPSC_DIV4
-  *         @arg @ref LL_TIM_ICPSC_DIV8
-  * @retval Input capture prescaler ratio (1, 2, 4 or 8)
-  */
-#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__)  \
-  ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
-
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
-  * @{
-  */
-
-/** @defgroup TIM_LL_EF_Time_Base Time Base configuration
-  * @{
-  */
-/**
-  * @brief  Enable timer counter.
-  * @rmtoll CR1          CEN           LL_TIM_EnableCounter
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->CR1, TIM_CR1_CEN);
-}
-
-/**
-  * @brief  Disable timer counter.
-  * @rmtoll CR1          CEN           LL_TIM_DisableCounter
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
-}
-
-/**
-  * @brief  Indicates whether the timer counter is enabled.
-  * @rmtoll CR1          CEN           LL_TIM_IsEnabledCounter
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable update event generation.
-  * @rmtoll CR1          UDIS          LL_TIM_EnableUpdateEvent
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
-}
-
-/**
-  * @brief  Disable update event generation.
-  * @rmtoll CR1          UDIS          LL_TIM_DisableUpdateEvent
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
-}
-
-/**
-  * @brief  Indicates whether update event generation is enabled.
-  * @rmtoll CR1          UDIS          LL_TIM_IsEnabledUpdateEvent
-  * @param  TIMx Timer instance
-  * @retval Inverted state of bit (0 or 1).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set update event source
-  * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
-  *       generate an update interrupt or DMA request if enabled:
-  *        - Counter overflow/underflow
-  *        - Setting the UG bit
-  *        - Update generation through the slave mode controller
-  * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
-  *       overflow/underflow generates an update interrupt or DMA request if enabled.
-  * @rmtoll CR1          URS           LL_TIM_SetUpdateSource
-  * @param  TIMx Timer instance
-  * @param  UpdateSource This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_UPDATESOURCE_REGULAR
-  *         @arg @ref LL_TIM_UPDATESOURCE_COUNTER
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
-{
-  MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
-}
-
-/**
-  * @brief  Get actual event update source
-  * @rmtoll CR1          URS           LL_TIM_GetUpdateSource
-  * @param  TIMx Timer instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_TIM_UPDATESOURCE_REGULAR
-  *         @arg @ref LL_TIM_UPDATESOURCE_COUNTER
-  */
-__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
-}
-
-/**
-  * @brief  Set one pulse mode (one shot v.s. repetitive).
-  * @rmtoll CR1          OPM           LL_TIM_SetOnePulseMode
-  * @param  TIMx Timer instance
-  * @param  OnePulseMode This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
-  *         @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
-{
-  MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
-}
-
-/**
-  * @brief  Get actual one pulse mode.
-  * @rmtoll CR1          OPM           LL_TIM_GetOnePulseMode
-  * @param  TIMx Timer instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
-  *         @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
-  */
-__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
-}
-
-/**
-  * @brief  Set the timer counter counting mode.
-  * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
-  *       check whether or not the counter mode selection feature is supported
-  *       by a timer instance.
-  * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
-  *       requires a timer reset to avoid unexpected direction
-  *       due to DIR bit readonly in center aligned mode.
-  * @rmtoll CR1          DIR           LL_TIM_SetCounterMode\n
-  *         CR1          CMS           LL_TIM_SetCounterMode
-  * @param  TIMx Timer instance
-  * @param  CounterMode This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_COUNTERMODE_UP
-  *         @arg @ref LL_TIM_COUNTERMODE_DOWN
-  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
-  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
-  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
-{
-  MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
-}
-
-/**
-  * @brief  Get actual counter mode.
-  * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
-  *       check whether or not the counter mode selection feature is supported
-  *       by a timer instance.
-  * @rmtoll CR1          DIR           LL_TIM_GetCounterMode\n
-  *         CR1          CMS           LL_TIM_GetCounterMode
-  * @param  TIMx Timer instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_TIM_COUNTERMODE_UP
-  *         @arg @ref LL_TIM_COUNTERMODE_DOWN
-  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
-  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
-  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
-  */
-__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx)
-{
-  uint32_t counter_mode;
-
-  counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
-
-  if (counter_mode == 0U)
-  {
-    counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
-  }
-
-  return counter_mode;
-}
-
-/**
-  * @brief  Enable auto-reload (ARR) preload.
-  * @rmtoll CR1          ARPE          LL_TIM_EnableARRPreload
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
-}
-
-/**
-  * @brief  Disable auto-reload (ARR) preload.
-  * @rmtoll CR1          ARPE          LL_TIM_DisableARRPreload
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
-}
-
-/**
-  * @brief  Indicates whether auto-reload (ARR) preload is enabled.
-  * @rmtoll CR1          ARPE          LL_TIM_IsEnabledARRPreload
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set the division ratio between the timer clock  and the sampling clock used by the dead-time generators
-  *         (when supported) and the digital filters.
-  * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
-  *       whether or not the clock division feature is supported by the timer
-  *       instance.
-  * @rmtoll CR1          CKD           LL_TIM_SetClockDivision
-  * @param  TIMx Timer instance
-  * @param  ClockDivision This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
-  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
-  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
-{
-  MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
-}
-
-/**
-  * @brief  Get the actual division ratio between the timer clock  and the sampling clock used by the dead-time
-  *         generators (when supported) and the digital filters.
-  * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
-  *       whether or not the clock division feature is supported by the timer
-  *       instance.
-  * @rmtoll CR1          CKD           LL_TIM_GetClockDivision
-  * @param  TIMx Timer instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
-  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
-  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
-  */
-__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
-}
-
-/**
-  * @brief  Set the counter value.
-  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a 32 bits counter.
-  * @rmtoll CNT          CNT           LL_TIM_SetCounter
-  * @param  TIMx Timer instance
-  * @param  Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
-{
-  WRITE_REG(TIMx->CNT, Counter);
-}
-
-/**
-  * @brief  Get the counter value.
-  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a 32 bits counter.
-  * @rmtoll CNT          CNT           LL_TIM_GetCounter
-  * @param  TIMx Timer instance
-  * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
-  */
-__STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_REG(TIMx->CNT));
-}
-
-/**
-  * @brief  Get the current direction of the counter
-  * @rmtoll CR1          DIR           LL_TIM_GetDirection
-  * @param  TIMx Timer instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_TIM_COUNTERDIRECTION_UP
-  *         @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
-  */
-__STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
-}
-
-/**
-  * @brief  Set the prescaler value.
-  * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
-  * @note The prescaler can be changed on the fly as this control register is buffered. The new
-  *       prescaler ratio is taken into account at the next update event.
-  * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
-  * @rmtoll PSC          PSC           LL_TIM_SetPrescaler
-  * @param  TIMx Timer instance
-  * @param  Prescaler between Min_Data=0 and Max_Data=65535
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
-{
-  WRITE_REG(TIMx->PSC, Prescaler);
-}
-
-/**
-  * @brief  Get the prescaler value.
-  * @rmtoll PSC          PSC           LL_TIM_GetPrescaler
-  * @param  TIMx Timer instance
-  * @retval  Prescaler value between Min_Data=0 and Max_Data=65535
-  */
-__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_REG(TIMx->PSC));
-}
-
-/**
-  * @brief  Set the auto-reload value.
-  * @note The counter is blocked while the auto-reload value is null.
-  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a 32 bits counter.
-  * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
-  * @rmtoll ARR          ARR           LL_TIM_SetAutoReload
-  * @param  TIMx Timer instance
-  * @param  AutoReload between Min_Data=0 and Max_Data=65535
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
-{
-  WRITE_REG(TIMx->ARR, AutoReload);
-}
-
-/**
-  * @brief  Get the auto-reload value.
-  * @rmtoll ARR          ARR           LL_TIM_GetAutoReload
-  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a 32 bits counter.
-  * @param  TIMx Timer instance
-  * @retval Auto-reload value
-  */
-__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_REG(TIMx->ARR));
-}
-
-/**
-  * @brief  Set the repetition counter value.
-  * @note For advanced timer instances RepetitionCounter can be up to 65535.
-  * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a repetition counter.
-  * @rmtoll RCR          REP           LL_TIM_SetRepetitionCounter
-  * @param  TIMx Timer instance
-  * @param  RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
-{
-  WRITE_REG(TIMx->RCR, RepetitionCounter);
-}
-
-/**
-  * @brief  Get the repetition counter value.
-  * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a repetition counter.
-  * @rmtoll RCR          REP           LL_TIM_GetRepetitionCounter
-  * @param  TIMx Timer instance
-  * @retval Repetition counter value
-  */
-__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_REG(TIMx->RCR));
-}
-
-/**
-  * @brief  Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
-  * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read
-  *       in an atomic way.
-  * @rmtoll CR1          UIFREMAP      LL_TIM_EnableUIFRemap
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
-}
-
-/**
-  * @brief  Disable update interrupt flag (UIF) remapping.
-  * @rmtoll CR1          UIFREMAP      LL_TIM_DisableUIFRemap
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
-}
-
-/**
-  * @brief  Indicate whether update interrupt flag (UIF) copy is set.
-  * @param  Counter Counter value
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(const uint32_t Counter)
-{
-  return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
-  * @{
-  */
-/**
-  * @brief  Enable  the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
-  * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
-  *       they are updated only when a commutation event (COM) occurs.
-  * @note Only on channels that have a complementary output.
-  * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance is able to generate a commutation event.
-  * @rmtoll CR2          CCPC          LL_TIM_CC_EnablePreload
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
-}
-
-/**
-  * @brief  Disable  the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
-  * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance is able to generate a commutation event.
-  * @rmtoll CR2          CCPC          LL_TIM_CC_DisablePreload
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
-}
-
-/**
-  * @brief  Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is enabled.
-  * @rmtoll CR2          CCPC          LL_TIM_CC_IsEnabledPreload
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
-  * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance is able to generate a commutation event.
-  * @rmtoll CR2          CCUS          LL_TIM_CC_SetUpdate
-  * @param  TIMx Timer instance
-  * @param  CCUpdateSource This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
-  *         @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
-{
-  MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
-}
-
-/**
-  * @brief  Set the trigger of the capture/compare DMA request.
-  * @rmtoll CR2          CCDS          LL_TIM_CC_SetDMAReqTrigger
-  * @param  TIMx Timer instance
-  * @param  DMAReqTrigger This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CCDMAREQUEST_CC
-  *         @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
-{
-  MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
-}
-
-/**
-  * @brief  Get actual trigger of the capture/compare DMA request.
-  * @rmtoll CR2          CCDS          LL_TIM_CC_GetDMAReqTrigger
-  * @param  TIMx Timer instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_TIM_CCDMAREQUEST_CC
-  *         @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
-  */
-__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
-}
-
-/**
-  * @brief  Set the lock level to freeze the
-  *         configuration of several capture/compare parameters.
-  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
-  *       the lock mechanism is supported by a timer instance.
-  * @rmtoll BDTR         LOCK          LL_TIM_CC_SetLockLevel
-  * @param  TIMx Timer instance
-  * @param  LockLevel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_LOCKLEVEL_OFF
-  *         @arg @ref LL_TIM_LOCKLEVEL_1
-  *         @arg @ref LL_TIM_LOCKLEVEL_2
-  *         @arg @ref LL_TIM_LOCKLEVEL_3
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
-{
-  MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
-}
-
-/**
-  * @brief  Enable capture/compare channels.
-  * @rmtoll CCER         CC1E          LL_TIM_CC_EnableChannel\n
-  *         CCER         CC1NE         LL_TIM_CC_EnableChannel\n
-  *         CCER         CC2E          LL_TIM_CC_EnableChannel\n
-  *         CCER         CC2NE         LL_TIM_CC_EnableChannel\n
-  *         CCER         CC3E          LL_TIM_CC_EnableChannel\n
-  *         CCER         CC3NE         LL_TIM_CC_EnableChannel\n
-  *         CCER         CC4E          LL_TIM_CC_EnableChannel\n
-  *         CCER         CC5E          LL_TIM_CC_EnableChannel\n
-  *         CCER         CC6E          LL_TIM_CC_EnableChannel
-  * @param  TIMx Timer instance
-  * @param  Channels This parameter can be a combination of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH1N
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH2N
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH3N
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  *         @arg @ref LL_TIM_CHANNEL_CH5
-  *         @arg @ref LL_TIM_CHANNEL_CH6
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
-{
-  SET_BIT(TIMx->CCER, Channels);
-}
-
-/**
-  * @brief  Disable capture/compare channels.
-  * @rmtoll CCER         CC1E          LL_TIM_CC_DisableChannel\n
-  *         CCER         CC1NE         LL_TIM_CC_DisableChannel\n
-  *         CCER         CC2E          LL_TIM_CC_DisableChannel\n
-  *         CCER         CC2NE         LL_TIM_CC_DisableChannel\n
-  *         CCER         CC3E          LL_TIM_CC_DisableChannel\n
-  *         CCER         CC3NE         LL_TIM_CC_DisableChannel\n
-  *         CCER         CC4E          LL_TIM_CC_DisableChannel\n
-  *         CCER         CC5E          LL_TIM_CC_DisableChannel\n
-  *         CCER         CC6E          LL_TIM_CC_DisableChannel
-  * @param  TIMx Timer instance
-  * @param  Channels This parameter can be a combination of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH1N
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH2N
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH3N
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  *         @arg @ref LL_TIM_CHANNEL_CH5
-  *         @arg @ref LL_TIM_CHANNEL_CH6
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
-{
-  CLEAR_BIT(TIMx->CCER, Channels);
-}
-
-/**
-  * @brief  Indicate whether channel(s) is(are) enabled.
-  * @rmtoll CCER         CC1E          LL_TIM_CC_IsEnabledChannel\n
-  *         CCER         CC1NE         LL_TIM_CC_IsEnabledChannel\n
-  *         CCER         CC2E          LL_TIM_CC_IsEnabledChannel\n
-  *         CCER         CC2NE         LL_TIM_CC_IsEnabledChannel\n
-  *         CCER         CC3E          LL_TIM_CC_IsEnabledChannel\n
-  *         CCER         CC3NE         LL_TIM_CC_IsEnabledChannel\n
-  *         CCER         CC4E          LL_TIM_CC_IsEnabledChannel\n
-  *         CCER         CC5E          LL_TIM_CC_IsEnabledChannel\n
-  *         CCER         CC6E          LL_TIM_CC_IsEnabledChannel
-  * @param  TIMx Timer instance
-  * @param  Channels This parameter can be a combination of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH1N
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH2N
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH3N
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  *         @arg @ref LL_TIM_CHANNEL_CH5
-  *         @arg @ref LL_TIM_CHANNEL_CH6
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels)
-{
-  return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
-  * @{
-  */
-/**
-  * @brief  Configure an output channel.
-  * @rmtoll CCMR1        CC1S          LL_TIM_OC_ConfigOutput\n
-  *         CCMR1        CC2S          LL_TIM_OC_ConfigOutput\n
-  *         CCMR2        CC3S          LL_TIM_OC_ConfigOutput\n
-  *         CCMR2        CC4S          LL_TIM_OC_ConfigOutput\n
-  *         CCMR3        CC5S          LL_TIM_OC_ConfigOutput\n
-  *         CCMR3        CC6S          LL_TIM_OC_ConfigOutput\n
-  *         CCER         CC1P          LL_TIM_OC_ConfigOutput\n
-  *         CCER         CC2P          LL_TIM_OC_ConfigOutput\n
-  *         CCER         CC3P          LL_TIM_OC_ConfigOutput\n
-  *         CCER         CC4P          LL_TIM_OC_ConfigOutput\n
-  *         CCER         CC5P          LL_TIM_OC_ConfigOutput\n
-  *         CCER         CC6P          LL_TIM_OC_ConfigOutput\n
-  *         CR2          OIS1          LL_TIM_OC_ConfigOutput\n
-  *         CR2          OIS2          LL_TIM_OC_ConfigOutput\n
-  *         CR2          OIS3          LL_TIM_OC_ConfigOutput\n
-  *         CR2          OIS4          LL_TIM_OC_ConfigOutput\n
-  *         CR2          OIS5          LL_TIM_OC_ConfigOutput\n
-  *         CR2          OIS6          LL_TIM_OC_ConfigOutput
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  *         @arg @ref LL_TIM_CHANNEL_CH5
-  *         @arg @ref LL_TIM_CHANNEL_CH6
-  * @param  Configuration This parameter must be a combination of all the following values:
-  *         @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
-  *         @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
-  MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
-             (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
-  MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
-             (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
-}
-
-/**
-  * @brief  Define the behavior of the output reference signal OCxREF from which
-  *         OCx and OCxN (when relevant) are derived.
-  * @rmtoll CCMR1        OC1M          LL_TIM_OC_SetMode\n
-  *         CCMR1        OC2M          LL_TIM_OC_SetMode\n
-  *         CCMR2        OC3M          LL_TIM_OC_SetMode\n
-  *         CCMR2        OC4M          LL_TIM_OC_SetMode\n
-  *         CCMR3        OC5M          LL_TIM_OC_SetMode\n
-  *         CCMR3        OC6M          LL_TIM_OC_SetMode
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  *         @arg @ref LL_TIM_CHANNEL_CH5
-  *         @arg @ref LL_TIM_CHANNEL_CH6
-  * @param  Mode This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_OCMODE_FROZEN
-  *         @arg @ref LL_TIM_OCMODE_ACTIVE
-  *         @arg @ref LL_TIM_OCMODE_INACTIVE
-  *         @arg @ref LL_TIM_OCMODE_TOGGLE
-  *         @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
-  *         @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
-  *         @arg @ref LL_TIM_OCMODE_PWM1
-  *         @arg @ref LL_TIM_OCMODE_PWM2
-  *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
-  *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
-  *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
-  *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
-  *         @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1
-  *         @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M  | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
-}
-
-/**
-  * @brief  Get the output compare mode of an output channel.
-  * @rmtoll CCMR1        OC1M          LL_TIM_OC_GetMode\n
-  *         CCMR1        OC2M          LL_TIM_OC_GetMode\n
-  *         CCMR2        OC3M          LL_TIM_OC_GetMode\n
-  *         CCMR2        OC4M          LL_TIM_OC_GetMode\n
-  *         CCMR3        OC5M          LL_TIM_OC_GetMode\n
-  *         CCMR3        OC6M          LL_TIM_OC_GetMode
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  *         @arg @ref LL_TIM_CHANNEL_CH5
-  *         @arg @ref LL_TIM_CHANNEL_CH6
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_TIM_OCMODE_FROZEN
-  *         @arg @ref LL_TIM_OCMODE_ACTIVE
-  *         @arg @ref LL_TIM_OCMODE_INACTIVE
-  *         @arg @ref LL_TIM_OCMODE_TOGGLE
-  *         @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
-  *         @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
-  *         @arg @ref LL_TIM_OCMODE_PWM1
-  *         @arg @ref LL_TIM_OCMODE_PWM2
-  *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
-  *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
-  *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
-  *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
-  *         @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1
-  *         @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2
-  */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
-}
-
-/**
-  * @brief  Set the polarity of an output channel.
-  * @rmtoll CCER         CC1P          LL_TIM_OC_SetPolarity\n
-  *         CCER         CC1NP         LL_TIM_OC_SetPolarity\n
-  *         CCER         CC2P          LL_TIM_OC_SetPolarity\n
-  *         CCER         CC2NP         LL_TIM_OC_SetPolarity\n
-  *         CCER         CC3P          LL_TIM_OC_SetPolarity\n
-  *         CCER         CC3NP         LL_TIM_OC_SetPolarity\n
-  *         CCER         CC4P          LL_TIM_OC_SetPolarity\n
-  *         CCER         CC5P          LL_TIM_OC_SetPolarity\n
-  *         CCER         CC6P          LL_TIM_OC_SetPolarity
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH1N
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH2N
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH3N
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  *         @arg @ref LL_TIM_CHANNEL_CH5
-  *         @arg @ref LL_TIM_CHANNEL_CH6
-  * @param  Polarity This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_OCPOLARITY_HIGH
-  *         @arg @ref LL_TIM_OCPOLARITY_LOW
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),  Polarity << SHIFT_TAB_CCxP[iChannel]);
-}
-
-/**
-  * @brief  Get the polarity of an output channel.
-  * @rmtoll CCER         CC1P          LL_TIM_OC_GetPolarity\n
-  *         CCER         CC1NP         LL_TIM_OC_GetPolarity\n
-  *         CCER         CC2P          LL_TIM_OC_GetPolarity\n
-  *         CCER         CC2NP         LL_TIM_OC_GetPolarity\n
-  *         CCER         CC3P          LL_TIM_OC_GetPolarity\n
-  *         CCER         CC3NP         LL_TIM_OC_GetPolarity\n
-  *         CCER         CC4P          LL_TIM_OC_GetPolarity\n
-  *         CCER         CC5P          LL_TIM_OC_GetPolarity\n
-  *         CCER         CC6P          LL_TIM_OC_GetPolarity
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH1N
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH2N
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH3N
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  *         @arg @ref LL_TIM_CHANNEL_CH5
-  *         @arg @ref LL_TIM_CHANNEL_CH6
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_TIM_OCPOLARITY_HIGH
-  *         @arg @ref LL_TIM_OCPOLARITY_LOW
-  */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
-}
-
-/**
-  * @brief  Set the IDLE state of an output channel
-  * @note This function is significant only for the timer instances
-  *       supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
-  *       can be used to check whether or not a timer instance provides
-  *       a break input.
-  * @rmtoll CR2         OIS1          LL_TIM_OC_SetIdleState\n
-  *         CR2         OIS2N         LL_TIM_OC_SetIdleState\n
-  *         CR2         OIS2          LL_TIM_OC_SetIdleState\n
-  *         CR2         OIS2N         LL_TIM_OC_SetIdleState\n
-  *         CR2         OIS3          LL_TIM_OC_SetIdleState\n
-  *         CR2         OIS3N         LL_TIM_OC_SetIdleState\n
-  *         CR2         OIS4          LL_TIM_OC_SetIdleState\n
-  *         CR2         OIS5          LL_TIM_OC_SetIdleState\n
-  *         CR2         OIS6          LL_TIM_OC_SetIdleState
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH1N
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH2N
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH3N
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  *         @arg @ref LL_TIM_CHANNEL_CH5
-  *         @arg @ref LL_TIM_CHANNEL_CH6
-  * @param  IdleState This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_OCIDLESTATE_LOW
-  *         @arg @ref LL_TIM_OCIDLESTATE_HIGH
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),  IdleState << SHIFT_TAB_OISx[iChannel]);
-}
-
-/**
-  * @brief  Get the IDLE state of an output channel
-  * @rmtoll CR2         OIS1          LL_TIM_OC_GetIdleState\n
-  *         CR2         OIS2N         LL_TIM_OC_GetIdleState\n
-  *         CR2         OIS2          LL_TIM_OC_GetIdleState\n
-  *         CR2         OIS2N         LL_TIM_OC_GetIdleState\n
-  *         CR2         OIS3          LL_TIM_OC_GetIdleState\n
-  *         CR2         OIS3N         LL_TIM_OC_GetIdleState\n
-  *         CR2         OIS4          LL_TIM_OC_GetIdleState\n
-  *         CR2         OIS5          LL_TIM_OC_GetIdleState\n
-  *         CR2         OIS6          LL_TIM_OC_GetIdleState
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH1N
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH2N
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH3N
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  *         @arg @ref LL_TIM_CHANNEL_CH5
-  *         @arg @ref LL_TIM_CHANNEL_CH6
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_TIM_OCIDLESTATE_LOW
-  *         @arg @ref LL_TIM_OCIDLESTATE_HIGH
-  */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
-}
-
-/**
-  * @brief  Enable fast mode for the output channel.
-  * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
-  * @rmtoll CCMR1        OC1FE          LL_TIM_OC_EnableFast\n
-  *         CCMR1        OC2FE          LL_TIM_OC_EnableFast\n
-  *         CCMR2        OC3FE          LL_TIM_OC_EnableFast\n
-  *         CCMR2        OC4FE          LL_TIM_OC_EnableFast\n
-  *         CCMR3        OC5FE          LL_TIM_OC_EnableFast\n
-  *         CCMR3        OC6FE          LL_TIM_OC_EnableFast
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  *         @arg @ref LL_TIM_CHANNEL_CH5
-  *         @arg @ref LL_TIM_CHANNEL_CH6
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
-
-}
-
-/**
-  * @brief  Disable fast mode for the output channel.
-  * @rmtoll CCMR1        OC1FE          LL_TIM_OC_DisableFast\n
-  *         CCMR1        OC2FE          LL_TIM_OC_DisableFast\n
-  *         CCMR2        OC3FE          LL_TIM_OC_DisableFast\n
-  *         CCMR2        OC4FE          LL_TIM_OC_DisableFast\n
-  *         CCMR3        OC5FE          LL_TIM_OC_DisableFast\n
-  *         CCMR3        OC6FE          LL_TIM_OC_DisableFast
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  *         @arg @ref LL_TIM_CHANNEL_CH5
-  *         @arg @ref LL_TIM_CHANNEL_CH6
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
-
-}
-
-/**
-  * @brief  Indicates whether fast mode is enabled for the output channel.
-  * @rmtoll CCMR1        OC1FE          LL_TIM_OC_IsEnabledFast\n
-  *         CCMR1        OC2FE          LL_TIM_OC_IsEnabledFast\n
-  *         CCMR2        OC3FE          LL_TIM_OC_IsEnabledFast\n
-  *         CCMR2        OC4FE          LL_TIM_OC_IsEnabledFast\n
-  *         CCMR3        OC5FE          LL_TIM_OC_IsEnabledFast\n
-  *         CCMR3        OC6FE          LL_TIM_OC_IsEnabledFast
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  *         @arg @ref LL_TIM_CHANNEL_CH5
-  *         @arg @ref LL_TIM_CHANNEL_CH6
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
-  return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable compare register (TIMx_CCRx) preload for the output channel.
-  * @rmtoll CCMR1        OC1PE          LL_TIM_OC_EnablePreload\n
-  *         CCMR1        OC2PE          LL_TIM_OC_EnablePreload\n
-  *         CCMR2        OC3PE          LL_TIM_OC_EnablePreload\n
-  *         CCMR2        OC4PE          LL_TIM_OC_EnablePreload\n
-  *         CCMR3        OC5PE          LL_TIM_OC_EnablePreload\n
-  *         CCMR3        OC6PE          LL_TIM_OC_EnablePreload
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  *         @arg @ref LL_TIM_CHANNEL_CH5
-  *         @arg @ref LL_TIM_CHANNEL_CH6
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
-}
-
-/**
-  * @brief  Disable compare register (TIMx_CCRx) preload for the output channel.
-  * @rmtoll CCMR1        OC1PE          LL_TIM_OC_DisablePreload\n
-  *         CCMR1        OC2PE          LL_TIM_OC_DisablePreload\n
-  *         CCMR2        OC3PE          LL_TIM_OC_DisablePreload\n
-  *         CCMR2        OC4PE          LL_TIM_OC_DisablePreload\n
-  *         CCMR3        OC5PE          LL_TIM_OC_DisablePreload\n
-  *         CCMR3        OC6PE          LL_TIM_OC_DisablePreload
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  *         @arg @ref LL_TIM_CHANNEL_CH5
-  *         @arg @ref LL_TIM_CHANNEL_CH6
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
-}
-
-/**
-  * @brief  Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
-  * @rmtoll CCMR1        OC1PE          LL_TIM_OC_IsEnabledPreload\n
-  *         CCMR1        OC2PE          LL_TIM_OC_IsEnabledPreload\n
-  *         CCMR2        OC3PE          LL_TIM_OC_IsEnabledPreload\n
-  *         CCMR2        OC4PE          LL_TIM_OC_IsEnabledPreload\n
-  *         CCMR3        OC5PE          LL_TIM_OC_IsEnabledPreload\n
-  *         CCMR3        OC6PE          LL_TIM_OC_IsEnabledPreload
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  *         @arg @ref LL_TIM_CHANNEL_CH5
-  *         @arg @ref LL_TIM_CHANNEL_CH6
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
-  return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable clearing the output channel on an external event.
-  * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
-  * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
-  *       or not a timer instance can clear the OCxREF signal on an external event.
-  * @rmtoll CCMR1        OC1CE          LL_TIM_OC_EnableClear\n
-  *         CCMR1        OC2CE          LL_TIM_OC_EnableClear\n
-  *         CCMR2        OC3CE          LL_TIM_OC_EnableClear\n
-  *         CCMR2        OC4CE          LL_TIM_OC_EnableClear\n
-  *         CCMR3        OC5CE          LL_TIM_OC_EnableClear\n
-  *         CCMR3        OC6CE          LL_TIM_OC_EnableClear
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  *         @arg @ref LL_TIM_CHANNEL_CH5
-  *         @arg @ref LL_TIM_CHANNEL_CH6
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
-}
-
-/**
-  * @brief  Disable clearing the output channel on an external event.
-  * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
-  *       or not a timer instance can clear the OCxREF signal on an external event.
-  * @rmtoll CCMR1        OC1CE          LL_TIM_OC_DisableClear\n
-  *         CCMR1        OC2CE          LL_TIM_OC_DisableClear\n
-  *         CCMR2        OC3CE          LL_TIM_OC_DisableClear\n
-  *         CCMR2        OC4CE          LL_TIM_OC_DisableClear\n
-  *         CCMR3        OC5CE          LL_TIM_OC_DisableClear\n
-  *         CCMR3        OC6CE          LL_TIM_OC_DisableClear
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  *         @arg @ref LL_TIM_CHANNEL_CH5
-  *         @arg @ref LL_TIM_CHANNEL_CH6
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
-}
-
-/**
-  * @brief  Indicates clearing the output channel on an external event is enabled for the output channel.
-  * @note This function enables clearing the output channel on an external event.
-  * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
-  * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
-  *       or not a timer instance can clear the OCxREF signal on an external event.
-  * @rmtoll CCMR1        OC1CE          LL_TIM_OC_IsEnabledClear\n
-  *         CCMR1        OC2CE          LL_TIM_OC_IsEnabledClear\n
-  *         CCMR2        OC3CE          LL_TIM_OC_IsEnabledClear\n
-  *         CCMR2        OC4CE          LL_TIM_OC_IsEnabledClear\n
-  *         CCMR3        OC5CE          LL_TIM_OC_IsEnabledClear\n
-  *         CCMR3        OC6CE          LL_TIM_OC_IsEnabledClear
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  *         @arg @ref LL_TIM_CHANNEL_CH5
-  *         @arg @ref LL_TIM_CHANNEL_CH6
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
-  return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of
-  *         the Ocx and OCxN signals).
-  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
-  *       dead-time insertion feature is supported by a timer instance.
-  * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
-  * @rmtoll BDTR         DTG           LL_TIM_OC_SetDeadTime
-  * @param  TIMx Timer instance
-  * @param  DeadTime between Min_Data=0 and Max_Data=255
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
-{
-  MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
-}
-
-/**
-  * @brief  Set compare value for output channel 1 (TIMx_CCR1).
-  * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
-  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a 32 bits counter.
-  * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
-  *       output channel 1 is supported by a timer instance.
-  * @rmtoll CCR1         CCR1          LL_TIM_OC_SetCompareCH1
-  * @param  TIMx Timer instance
-  * @param  CompareValue between Min_Data=0 and Max_Data=65535
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
-{
-  WRITE_REG(TIMx->CCR1, CompareValue);
-}
-
-/**
-  * @brief  Set compare value for output channel 2 (TIMx_CCR2).
-  * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
-  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a 32 bits counter.
-  * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
-  *       output channel 2 is supported by a timer instance.
-  * @rmtoll CCR2         CCR2          LL_TIM_OC_SetCompareCH2
-  * @param  TIMx Timer instance
-  * @param  CompareValue between Min_Data=0 and Max_Data=65535
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
-{
-  WRITE_REG(TIMx->CCR2, CompareValue);
-}
-
-/**
-  * @brief  Set compare value for output channel 3 (TIMx_CCR3).
-  * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
-  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a 32 bits counter.
-  * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
-  *       output channel is supported by a timer instance.
-  * @rmtoll CCR3         CCR3          LL_TIM_OC_SetCompareCH3
-  * @param  TIMx Timer instance
-  * @param  CompareValue between Min_Data=0 and Max_Data=65535
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
-{
-  WRITE_REG(TIMx->CCR3, CompareValue);
-}
-
-/**
-  * @brief  Set compare value for output channel 4 (TIMx_CCR4).
-  * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
-  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a 32 bits counter.
-  * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
-  *       output channel 4 is supported by a timer instance.
-  * @rmtoll CCR4         CCR4          LL_TIM_OC_SetCompareCH4
-  * @param  TIMx Timer instance
-  * @param  CompareValue between Min_Data=0 and Max_Data=65535
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
-{
-  WRITE_REG(TIMx->CCR4, CompareValue);
-}
-
-/**
-  * @brief  Set compare value for output channel 5 (TIMx_CCR5).
-  * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
-  *       output channel 5 is supported by a timer instance.
-  * @rmtoll CCR5         CCR5          LL_TIM_OC_SetCompareCH5
-  * @param  TIMx Timer instance
-  * @param  CompareValue between Min_Data=0 and Max_Data=65535
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
-{
-  MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue);
-}
-
-/**
-  * @brief  Set compare value for output channel 6 (TIMx_CCR6).
-  * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
-  *       output channel 6 is supported by a timer instance.
-  * @rmtoll CCR6         CCR6          LL_TIM_OC_SetCompareCH6
-  * @param  TIMx Timer instance
-  * @param  CompareValue between Min_Data=0 and Max_Data=65535
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
-{
-  WRITE_REG(TIMx->CCR6, CompareValue);
-}
-
-/**
-  * @brief  Get compare value (TIMx_CCR1) set for  output channel 1.
-  * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
-  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a 32 bits counter.
-  * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
-  *       output channel 1 is supported by a timer instance.
-  * @rmtoll CCR1         CCR1          LL_TIM_OC_GetCompareCH1
-  * @param  TIMx Timer instance
-  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
-  */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_REG(TIMx->CCR1));
-}
-
-/**
-  * @brief  Get compare value (TIMx_CCR2) set for  output channel 2.
-  * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
-  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a 32 bits counter.
-  * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
-  *       output channel 2 is supported by a timer instance.
-  * @rmtoll CCR2         CCR2          LL_TIM_OC_GetCompareCH2
-  * @param  TIMx Timer instance
-  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
-  */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_REG(TIMx->CCR2));
-}
-
-/**
-  * @brief  Get compare value (TIMx_CCR3) set for  output channel 3.
-  * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
-  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a 32 bits counter.
-  * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
-  *       output channel 3 is supported by a timer instance.
-  * @rmtoll CCR3         CCR3          LL_TIM_OC_GetCompareCH3
-  * @param  TIMx Timer instance
-  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
-  */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_REG(TIMx->CCR3));
-}
-
-/**
-  * @brief  Get compare value (TIMx_CCR4) set for  output channel 4.
-  * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
-  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a 32 bits counter.
-  * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
-  *       output channel 4 is supported by a timer instance.
-  * @rmtoll CCR4         CCR4          LL_TIM_OC_GetCompareCH4
-  * @param  TIMx Timer instance
-  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
-  */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_REG(TIMx->CCR4));
-}
-
-/**
-  * @brief  Get compare value (TIMx_CCR5) set for  output channel 5.
-  * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
-  *       output channel 5 is supported by a timer instance.
-  * @rmtoll CCR5         CCR5          LL_TIM_OC_GetCompareCH5
-  * @param  TIMx Timer instance
-  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
-  */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(const TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5));
-}
-
-/**
-  * @brief  Get compare value (TIMx_CCR6) set for  output channel 6.
-  * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
-  *       output channel 6 is supported by a timer instance.
-  * @rmtoll CCR6         CCR6          LL_TIM_OC_GetCompareCH6
-  * @param  TIMx Timer instance
-  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
-  */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(const TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_REG(TIMx->CCR6));
-}
-
-/**
-  * @brief  Select on which reference signal the OC5REF is combined to.
-  * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports the combined 3-phase PWM mode.
-  * @rmtoll CCR5         GC5C3          LL_TIM_SetCH5CombinedChannels\n
-  *         CCR5         GC5C2          LL_TIM_SetCH5CombinedChannels\n
-  *         CCR5         GC5C1          LL_TIM_SetCH5CombinedChannels
-  * @param  TIMx Timer instance
-  * @param  GroupCH5 This parameter can be a combination of the following values:
-  *         @arg @ref LL_TIM_GROUPCH5_NONE
-  *         @arg @ref LL_TIM_GROUPCH5_OC1REFC
-  *         @arg @ref LL_TIM_GROUPCH5_OC2REFC
-  *         @arg @ref LL_TIM_GROUPCH5_OC3REFC
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
-{
-  MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
-  * @{
-  */
-/**
-  * @brief  Configure input channel.
-  * @rmtoll CCMR1        CC1S          LL_TIM_IC_Config\n
-  *         CCMR1        IC1PSC        LL_TIM_IC_Config\n
-  *         CCMR1        IC1F          LL_TIM_IC_Config\n
-  *         CCMR1        CC2S          LL_TIM_IC_Config\n
-  *         CCMR1        IC2PSC        LL_TIM_IC_Config\n
-  *         CCMR1        IC2F          LL_TIM_IC_Config\n
-  *         CCMR2        CC3S          LL_TIM_IC_Config\n
-  *         CCMR2        IC3PSC        LL_TIM_IC_Config\n
-  *         CCMR2        IC3F          LL_TIM_IC_Config\n
-  *         CCMR2        CC4S          LL_TIM_IC_Config\n
-  *         CCMR2        IC4PSC        LL_TIM_IC_Config\n
-  *         CCMR2        IC4F          LL_TIM_IC_Config\n
-  *         CCER         CC1P          LL_TIM_IC_Config\n
-  *         CCER         CC1NP         LL_TIM_IC_Config\n
-  *         CCER         CC2P          LL_TIM_IC_Config\n
-  *         CCER         CC2NP         LL_TIM_IC_Config\n
-  *         CCER         CC3P          LL_TIM_IC_Config\n
-  *         CCER         CC3NP         LL_TIM_IC_Config\n
-  *         CCER         CC4P          LL_TIM_IC_Config\n
-  *         CCER         CC4NP         LL_TIM_IC_Config
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @param  Configuration This parameter must be a combination of all the following values:
-  *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
-  *         @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
-  *         @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
-             ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S))                \
-             << SHIFT_TAB_ICxx[iChannel]);
-  MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
-             (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
-}
-
-/**
-  * @brief  Set the active input.
-  * @rmtoll CCMR1        CC1S          LL_TIM_IC_SetActiveInput\n
-  *         CCMR1        CC2S          LL_TIM_IC_SetActiveInput\n
-  *         CCMR2        CC3S          LL_TIM_IC_SetActiveInput\n
-  *         CCMR2        CC4S          LL_TIM_IC_SetActiveInput
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @param  ICActiveInput This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
-  *         @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
-  *         @arg @ref LL_TIM_ACTIVEINPUT_TRC
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
-}
-
-/**
-  * @brief  Get the current active input.
-  * @rmtoll CCMR1        CC1S          LL_TIM_IC_GetActiveInput\n
-  *         CCMR1        CC2S          LL_TIM_IC_GetActiveInput\n
-  *         CCMR2        CC3S          LL_TIM_IC_GetActiveInput\n
-  *         CCMR2        CC4S          LL_TIM_IC_GetActiveInput
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
-  *         @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
-  *         @arg @ref LL_TIM_ACTIVEINPUT_TRC
-  */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
-}
-
-/**
-  * @brief  Set the prescaler of input channel.
-  * @rmtoll CCMR1        IC1PSC        LL_TIM_IC_SetPrescaler\n
-  *         CCMR1        IC2PSC        LL_TIM_IC_SetPrescaler\n
-  *         CCMR2        IC3PSC        LL_TIM_IC_SetPrescaler\n
-  *         CCMR2        IC4PSC        LL_TIM_IC_SetPrescaler
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @param  ICPrescaler This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_ICPSC_DIV1
-  *         @arg @ref LL_TIM_ICPSC_DIV2
-  *         @arg @ref LL_TIM_ICPSC_DIV4
-  *         @arg @ref LL_TIM_ICPSC_DIV8
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
-}
-
-/**
-  * @brief  Get the current prescaler value acting on an  input channel.
-  * @rmtoll CCMR1        IC1PSC        LL_TIM_IC_GetPrescaler\n
-  *         CCMR1        IC2PSC        LL_TIM_IC_GetPrescaler\n
-  *         CCMR2        IC3PSC        LL_TIM_IC_GetPrescaler\n
-  *         CCMR2        IC4PSC        LL_TIM_IC_GetPrescaler
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_TIM_ICPSC_DIV1
-  *         @arg @ref LL_TIM_ICPSC_DIV2
-  *         @arg @ref LL_TIM_ICPSC_DIV4
-  *         @arg @ref LL_TIM_ICPSC_DIV8
-  */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
-}
-
-/**
-  * @brief  Set the input filter duration.
-  * @rmtoll CCMR1        IC1F          LL_TIM_IC_SetFilter\n
-  *         CCMR1        IC2F          LL_TIM_IC_SetFilter\n
-  *         CCMR2        IC3F          LL_TIM_IC_SetFilter\n
-  *         CCMR2        IC4F          LL_TIM_IC_SetFilter
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @param  ICFilter This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV1
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
-}
-
-/**
-  * @brief  Get the input filter duration.
-  * @rmtoll CCMR1        IC1F          LL_TIM_IC_GetFilter\n
-  *         CCMR1        IC2F          LL_TIM_IC_GetFilter\n
-  *         CCMR2        IC3F          LL_TIM_IC_GetFilter\n
-  *         CCMR2        IC4F          LL_TIM_IC_GetFilter
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV1
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
-  */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
-}
-
-/**
-  * @brief  Set the input channel polarity.
-  * @rmtoll CCER         CC1P          LL_TIM_IC_SetPolarity\n
-  *         CCER         CC1NP         LL_TIM_IC_SetPolarity\n
-  *         CCER         CC2P          LL_TIM_IC_SetPolarity\n
-  *         CCER         CC2NP         LL_TIM_IC_SetPolarity\n
-  *         CCER         CC3P          LL_TIM_IC_SetPolarity\n
-  *         CCER         CC3NP         LL_TIM_IC_SetPolarity\n
-  *         CCER         CC4P          LL_TIM_IC_SetPolarity\n
-  *         CCER         CC4NP         LL_TIM_IC_SetPolarity
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @param  ICPolarity This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_IC_POLARITY_RISING
-  *         @arg @ref LL_TIM_IC_POLARITY_FALLING
-  *         @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
-             ICPolarity << SHIFT_TAB_CCxP[iChannel]);
-}
-
-/**
-  * @brief  Get the current input channel polarity.
-  * @rmtoll CCER         CC1P          LL_TIM_IC_GetPolarity\n
-  *         CCER         CC1NP         LL_TIM_IC_GetPolarity\n
-  *         CCER         CC2P          LL_TIM_IC_GetPolarity\n
-  *         CCER         CC2NP         LL_TIM_IC_GetPolarity\n
-  *         CCER         CC3P          LL_TIM_IC_GetPolarity\n
-  *         CCER         CC3NP         LL_TIM_IC_GetPolarity\n
-  *         CCER         CC4P          LL_TIM_IC_GetPolarity\n
-  *         CCER         CC4NP         LL_TIM_IC_GetPolarity
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_TIM_IC_POLARITY_RISING
-  *         @arg @ref LL_TIM_IC_POLARITY_FALLING
-  *         @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
-  */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
-          SHIFT_TAB_CCxP[iChannel]);
-}
-
-/**
-  * @brief  Connect the TIMx_CH1, CH2 and CH3 pins  to the TI1 input (XOR combination).
-  * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance provides an XOR input.
-  * @rmtoll CR2          TI1S          LL_TIM_IC_EnableXORCombination
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
-}
-
-/**
-  * @brief  Disconnect the TIMx_CH1, CH2 and CH3 pins  from the TI1 input.
-  * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance provides an XOR input.
-  * @rmtoll CR2          TI1S          LL_TIM_IC_DisableXORCombination
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
-}
-
-/**
-  * @brief  Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
-  * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
-  * a timer instance provides an XOR input.
-  * @rmtoll CR2          TI1S          LL_TIM_IC_IsEnabledXORCombination
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get captured value for input channel 1.
-  * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
-  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a 32 bits counter.
-  * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
-  *       input channel 1 is supported by a timer instance.
-  * @rmtoll CCR1         CCR1          LL_TIM_IC_GetCaptureCH1
-  * @param  TIMx Timer instance
-  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
-  */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_REG(TIMx->CCR1));
-}
-
-/**
-  * @brief  Get captured value for input channel 2.
-  * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
-  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a 32 bits counter.
-  * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
-  *       input channel 2 is supported by a timer instance.
-  * @rmtoll CCR2         CCR2          LL_TIM_IC_GetCaptureCH2
-  * @param  TIMx Timer instance
-  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
-  */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_REG(TIMx->CCR2));
-}
-
-/**
-  * @brief  Get captured value for input channel 3.
-  * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
-  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a 32 bits counter.
-  * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
-  *       input channel 3 is supported by a timer instance.
-  * @rmtoll CCR3         CCR3          LL_TIM_IC_GetCaptureCH3
-  * @param  TIMx Timer instance
-  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
-  */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_REG(TIMx->CCR3));
-}
-
-/**
-  * @brief  Get captured value for input channel 4.
-  * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
-  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a 32 bits counter.
-  * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
-  *       input channel 4 is supported by a timer instance.
-  * @rmtoll CCR4         CCR4          LL_TIM_IC_GetCaptureCH4
-  * @param  TIMx Timer instance
-  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
-  */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_REG(TIMx->CCR4));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
-  * @{
-  */
-/**
-  * @brief  Enable external clock mode 2.
-  * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
-  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports external clock mode2.
-  * @rmtoll SMCR         ECE           LL_TIM_EnableExternalClock
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
-}
-
-/**
-  * @brief  Disable external clock mode 2.
-  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports external clock mode2.
-  * @rmtoll SMCR         ECE           LL_TIM_DisableExternalClock
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
-}
-
-/**
-  * @brief  Indicate whether external clock mode 2 is enabled.
-  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports external clock mode2.
-  * @rmtoll SMCR         ECE           LL_TIM_IsEnabledExternalClock
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set the clock source of the counter clock.
-  * @note when selected clock source is external clock mode 1, the timer input
-  *       the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
-  *       function. This timer input must be configured by calling
-  *       the @ref LL_TIM_IC_Config() function.
-  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports external clock mode1.
-  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports external clock mode2.
-  * @rmtoll SMCR         SMS           LL_TIM_SetClockSource\n
-  *         SMCR         ECE           LL_TIM_SetClockSource
-  * @param  TIMx Timer instance
-  * @param  ClockSource This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
-  *         @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
-  *         @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
-{
-  MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
-}
-
-/**
-  * @brief  Set the encoder interface mode.
-  * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports the encoder mode.
-  * @rmtoll SMCR         SMS           LL_TIM_SetEncoderMode
-  * @param  TIMx Timer instance
-  * @param  EncoderMode This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_ENCODERMODE_X2_TI1
-  *         @arg @ref LL_TIM_ENCODERMODE_X2_TI2
-  *         @arg @ref LL_TIM_ENCODERMODE_X4_TI12
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
-{
-  MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
-  * @{
-  */
-/**
-  * @brief  Set the trigger output (TRGO) used for timer synchronization .
-  * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance can operate as a master timer.
-  * @rmtoll CR2          MMS           LL_TIM_SetTriggerOutput
-  * @param  TIMx Timer instance
-  * @param  TimerSynchronization This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_TRGO_RESET
-  *         @arg @ref LL_TIM_TRGO_ENABLE
-  *         @arg @ref LL_TIM_TRGO_UPDATE
-  *         @arg @ref LL_TIM_TRGO_CC1IF
-  *         @arg @ref LL_TIM_TRGO_OC1REF
-  *         @arg @ref LL_TIM_TRGO_OC2REF
-  *         @arg @ref LL_TIM_TRGO_OC3REF
-  *         @arg @ref LL_TIM_TRGO_OC4REF
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
-{
-  MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
-}
-
-/**
-  * @brief  Set the trigger output 2 (TRGO2) used for ADC synchronization .
-  * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance can be used for ADC synchronization.
-  * @rmtoll CR2          MMS2          LL_TIM_SetTriggerOutput2
-  * @param  TIMx Timer Instance
-  * @param  ADCSynchronization This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_TRGO2_RESET
-  *         @arg @ref LL_TIM_TRGO2_ENABLE
-  *         @arg @ref LL_TIM_TRGO2_UPDATE
-  *         @arg @ref LL_TIM_TRGO2_CC1F
-  *         @arg @ref LL_TIM_TRGO2_OC1
-  *         @arg @ref LL_TIM_TRGO2_OC2
-  *         @arg @ref LL_TIM_TRGO2_OC3
-  *         @arg @ref LL_TIM_TRGO2_OC4
-  *         @arg @ref LL_TIM_TRGO2_OC5
-  *         @arg @ref LL_TIM_TRGO2_OC6
-  *         @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
-  *         @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
-  *         @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
-  *         @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
-  *         @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
-  *         @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
-{
-  MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
-}
-
-/**
-  * @brief  Set the synchronization mode of a slave timer.
-  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance can operate as a slave timer.
-  * @rmtoll SMCR         SMS           LL_TIM_SetSlaveMode
-  * @param  TIMx Timer instance
-  * @param  SlaveMode This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_SLAVEMODE_DISABLED
-  *         @arg @ref LL_TIM_SLAVEMODE_RESET
-  *         @arg @ref LL_TIM_SLAVEMODE_GATED
-  *         @arg @ref LL_TIM_SLAVEMODE_TRIGGER
-  *         @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
-{
-  MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
-}
-
-/**
-  * @brief  Set the selects the trigger input to be used to synchronize the counter.
-  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance can operate as a slave timer.
-  * @rmtoll SMCR         TS            LL_TIM_SetTriggerInput
-  * @param  TIMx Timer instance
-  * @param  TriggerInput This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_TS_ITR0
-  *         @arg @ref LL_TIM_TS_ITR1
-  *         @arg @ref LL_TIM_TS_ITR2
-  *         @arg @ref LL_TIM_TS_ITR3
-  *         @arg @ref LL_TIM_TS_ITR4
-  *         @arg @ref LL_TIM_TS_ITR5
-  *         @arg @ref LL_TIM_TS_ITR6
-  *         @arg @ref LL_TIM_TS_ITR7
-  *         @arg @ref LL_TIM_TS_ITR8 (*)
-  *         @arg @ref LL_TIM_TS_ITR9 (*)
-  *         @arg @ref LL_TIM_TS_ITR10 (*)
-  *         @arg @ref LL_TIM_TS_ITR11 (*)
-  *         @arg @ref LL_TIM_TS_ITR12 (*)
-  *         @arg @ref LL_TIM_TS_ITR13 (*)
-  *         @arg @ref LL_TIM_TS_TI1F_ED
-  *         @arg @ref LL_TIM_TS_TI1FP1
-  *         @arg @ref LL_TIM_TS_TI2FP2
-  *         @arg @ref LL_TIM_TS_ETRF
-  *
-  *      (*)  Value not defined in all devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
-{
-  MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
-}
-
-/**
-  * @brief  Enable the Master/Slave mode.
-  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance can operate as a slave timer.
-  * @rmtoll SMCR         MSM           LL_TIM_EnableMasterSlaveMode
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
-}
-
-/**
-  * @brief  Disable the Master/Slave mode.
-  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance can operate as a slave timer.
-  * @rmtoll SMCR         MSM           LL_TIM_DisableMasterSlaveMode
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
-}
-
-/**
-  * @brief Indicates whether the Master/Slave mode is enabled.
-  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
-  * a timer instance can operate as a slave timer.
-  * @rmtoll SMCR         MSM           LL_TIM_IsEnabledMasterSlaveMode
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Configure the external trigger (ETR) input.
-  * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance provides an external trigger input.
-  * @rmtoll SMCR         ETP           LL_TIM_ConfigETR\n
-  *         SMCR         ETPS          LL_TIM_ConfigETR\n
-  *         SMCR         ETF           LL_TIM_ConfigETR
-  * @param  TIMx Timer instance
-  * @param  ETRPolarity This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
-  *         @arg @ref LL_TIM_ETR_POLARITY_INVERTED
-  * @param  ETRPrescaler This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV1
-  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV2
-  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV4
-  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV8
-  * @param  ETRFilter This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
-                                      uint32_t ETRFilter)
-{
-  MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
-}
-
-/**
-  * @brief  Select the external trigger (ETR) input source.
-  * @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or
-  *       not a timer instance supports ETR source selection.
-  * @rmtoll AF1          ETRSEL        LL_TIM_SetETRSource
-  * @param  TIMx Timer instance
-  * @param  ETRSource This parameter can be one of the following values:
-  *      For TIM1, the parameter is one of the following values:
-  *         @arg LL_TIM_TIM1_ETRSOURCE_GPIO:               TIM1_ETR is connected to GPIO
-  *         @arg LL_TIM_TIM1_ETRSOURCE_COMP1:              TIM1_ETR is connected to COMP1 output
-  *         @arg LL_TIM_TIM1_ETRSOURCE_COMP2:              TIM1_ETR is connected to COMP2 output
-  *         @arg LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1:          TIM1_ETR is connected to ADC1 AWD1
-  *         @arg LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2:          TIM1_ETR is connected to ADC1 AWD2
-  *         @arg LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3:          TIM1_ETR is connected to ADC1 AWD3
-  *         @arg LL_TIM_TIM1_ETRSOURCE_ADC3_AWD1:          TIM1_ETR is connected to ADC3 AWD1
-  *         @arg LL_TIM_TIM1_ETRSOURCE_ADC3_AWD2:          TIM1_ETR is connected to ADC3 AWD2
-  *         @arg LL_TIM_TIM1_ETRSOURCE_ADC3_AWD3:          TIM1_ETR is connected to ADC3 AWD3
-  *
-  *      For TIM2, the parameter is one of the following values:
-  *         @arg LL_TIM_TIM2_ETRSOURCE_GPIO:               TIM2_ETR is connected to GPIO
-  *         @arg LL_TIM_TIM2_ETRSOURCE_COMP1:              TIM2_ETR is connected to COMP1 output
-  *         @arg LL_TIM_TIM2_ETRSOURCE_COMP2:              TIM2_ETR is connected to COMP2 output
-  *         @arg LL_TIM_TIM2_ETRSOURCE_LSE:                TIM2_ETR is connected to LSE
-  *         @arg LL_TIM_TIM2_ETRSOURCE_SAI1_FSA:           TIM2_ETR is connected to SAI1 FS_A
-  *         @arg LL_TIM_TIM2_ETRSOURCE_SAI1_FSB:           TIM2_ETR is connected to SAI1 FS_B
-  *
-  *      For TIM3, the parameter is one of the following values:
-  *         @arg LL_TIM_TIM3_ETRSOURCE_GPIO:               TIM3_ETR is connected to GPIO
-  *         @arg LL_TIM_TIM3_ETRSOURCE_COMP1:              TIM3_ETR is connected to COMP1 output
-  *
-  *      For TIM5, the parameter is one of the following values:
-  *         @arg LL_TIM_TIM5_ETRSOURCE_GPIO:               TIM5_ETR is connected to GPIO
-  *         @arg LL_TIM_TIM5_ETRSOURCE_SAI2_FSA:           TIM5_ETR is connected to SAI2 FS_A (*)
-  *         @arg LL_TIM_TIM5_ETRSOURCE_SAI2_FSB:           TIM5_ETR is connected to SAI2 FS_B (*)
-  *         @arg LL_TIM_TIM5_ETRSOURCE_SAI4_FSA:           TIM5_ETR is connected to SAI2 FS_A (*)
-  *         @arg LL_TIM_TIM5_ETRSOURCE_SAI4_FSB:           TIM5_ETR is connected to SAI2 FS_B (*)
-  *
-  *      For TIM8, the parameter is one of the following values:
-  *         @arg LL_TIM_TIM8_ETRSOURCE_GPIO:               TIM8_ETR is connected to GPIO
-  *         @arg LL_TIM_TIM8_ETRSOURCE_COMP1:              TIM8_ETR is connected to COMP1 output
-  *         @arg LL_TIM_TIM8_ETRSOURCE_COMP2:              TIM8_ETR is connected to COMP2 output
-  *         @arg LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1:          TIM8_ETR is connected to ADC2 AWD1
-  *         @arg LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2:          TIM8_ETR is connected to ADC2 AWD2
-  *         @arg LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3:          TIM8_ETR is connected to ADC2 AWD3
-  *         @arg LL_TIM_TIM8_ETRSOURCE_ADC3_AWD1:          TIM8_ETR is connected to ADC3 AWD1
-  *         @arg LL_TIM_TIM8_ETRSOURCE_ADC3_AWD2:          TIM8_ETR is connected to ADC3 AWD2
-  *         @arg LL_TIM_TIM8_ETRSOURCE_ADC3_AWD3:          TIM8_ETR is connected to ADC3 AWD3
-  *
-  *      For TIM23, the parameter is one of the following values: (*)
-  *         @arg LL_TIM_TIM23_ETRSOURCE_GPIO               TIM23_ETR is connected to GPIO
-  *         @arg LL_TIM_TIM23_ETRSOURCE_COMP1              TIM23_ETR is connected to COMP1 output
-  *         @arg LL_TIM_TIM23_ETRSOURCE_COMP2              TIM23_ETR is connected to COMP2 output
-  *
-  *      For TIM24, the parameter is one of the following values: (*)
-  *        @arg LL_TIM_TIM24_ETRSOURCE_GPIO                TIM24_ETR is connected to GPIO
-  *        @arg LL_TIM_TIM24_ETRSOURCE_SAI4_FSA            TIM24_ETR is connected to SAI4 FS_A
-  *        @arg LL_TIM_TIM24_ETRSOURCE_SAI4_FSB            TIM24_ETR is connected to SAI4 FS_B
-  *        @arg LL_TIM_TIM24_ETRSOURCE_SAI1_FSA            TIM24_ETR is connected to SAI1 FS_A
-  *        @arg LL_TIM_TIM24_ETRSOURCE_SAI1_FSB            TIM24_ETR is connected to SAI1 FS_B
-  *
-  *      (*)  Value not defined in all devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource)
-{
-  MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EF_Break_Function Break function configuration
-  * @{
-  */
-/**
-  * @brief  Enable the break function.
-  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance provides a break input.
-  * @rmtoll BDTR         BKE           LL_TIM_EnableBRK
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
-}
-
-/**
-  * @brief  Disable the break function.
-  * @rmtoll BDTR         BKE           LL_TIM_DisableBRK
-  * @param  TIMx Timer instance
-  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance provides a break input.
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
-}
-
-#if defined(TIM_BDTR_BKBID)
-/**
-  * @brief  Configure the break input.
-  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance provides a break input.
-  * @note Bidirectional mode is only supported by advanced timer instances.
-  *       Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance is an advanced-control timer.
-  * @note In bidirectional mode (BKBID bit set), the Break input is configured both
-  *        in input mode and in open drain output mode. Any active Break event will
-  *        assert a low logic level on the Break input to indicate an internal break
-  *        event to external devices.
-  * @note When bidirectional mode isn't supported, BreakAFMode must be set to
-  *       LL_TIM_BREAK_AFMODE_INPUT.
-  * @rmtoll BDTR         BKP           LL_TIM_ConfigBRK\n
-  *         BDTR         BKF           LL_TIM_ConfigBRK\n
-  *         BDTR         BKBID         LL_TIM_ConfigBRK
-  * @param  TIMx Timer instance
-  * @param  BreakPolarity This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_BREAK_POLARITY_LOW
-  *         @arg @ref LL_TIM_BREAK_POLARITY_HIGH
-  * @param  BreakFilter This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
-  * @param  BreakAFMode This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_BREAK_AFMODE_INPUT
-  *         @arg @ref LL_TIM_BREAK_AFMODE_BIDIRECTIONAL
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter,
-                                      uint32_t BreakAFMode)
-{
-  MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF | TIM_BDTR_BKBID, BreakPolarity | BreakFilter | BreakAFMode);
-}
-
-#else
-/**
-  * @brief  Configure the break input.
-  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance provides a break input.
-  * @rmtoll BDTR         BKP           LL_TIM_ConfigBRK\n
-  *         BDTR         BKF           LL_TIM_ConfigBRK
-  * @param  TIMx Timer instance
-  * @param  BreakPolarity This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_BREAK_POLARITY_LOW
-  *         @arg @ref LL_TIM_BREAK_POLARITY_HIGH
-  * @param  BreakFilter This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity,
-                                      uint32_t BreakFilter)
-{
-  MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF, BreakPolarity | BreakFilter);
-}
-
-#endif /* TIM_BDTR_BKBID */
-#if defined(TIM_BDTR_BKBID)
-/**
-  * @brief  Disarm the break input (when it operates in bidirectional mode).
-  * @note  The break input can be disarmed only when it is configured in
-  *        bidirectional mode and when when MOE is reset.
-  * @note  Purpose is to be able to have the input voltage back to high-state,
-  *        whatever the time constant on the output .
-  * @rmtoll BDTR         BKDSRM        LL_TIM_DisarmBRK
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
-}
-
-#endif /*TIM_BDTR_BKBID */
-/**
-  * @brief  Enable the break 2 function.
-  * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance provides a second break input.
-  * @rmtoll BDTR         BK2E          LL_TIM_EnableBRK2
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
-}
-
-/**
-  * @brief  Disable the break  2 function.
-  * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance provides a second break input.
-  * @rmtoll BDTR         BK2E          LL_TIM_DisableBRK2
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
-}
-
-#if defined(TIM_BDTR_BKBID)
-/**
-  * @brief  Configure the break 2 input.
-  * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance provides a second break input.
-  * @note Bidirectional mode is only supported by advanced timer instances.
-  *       Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance is an advanced-control timer.
-  * @note In bidirectional mode (BK2BID bit set), the Break 2 input is configured both
-  *        in input mode and in open drain output mode. Any active Break event will
-  *        assert a low logic level on the Break 2 input to indicate an internal break
-  *        event to external devices.
-  * @note When bidirectional mode isn't supported, Break2AFMode must be set to
-  *       LL_TIM_BREAK2_AFMODE_INPUT.
-  * @rmtoll BDTR         BK2P          LL_TIM_ConfigBRK2\n
-  *         BDTR         BK2F          LL_TIM_ConfigBRK2\n
-  *         BDTR         BK2BID        LL_TIM_ConfigBRK2
-  * @param  TIMx Timer instance
-  * @param  Break2Polarity This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_BREAK2_POLARITY_LOW
-  *         @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
-  * @param  Break2Filter This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
-  * @param  Break2AFMode This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_BREAK2_AFMODE_INPUT
-  *         @arg @ref LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter,
-                                       uint32_t Break2AFMode)
-{
-  MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F | TIM_BDTR_BK2BID, Break2Polarity | Break2Filter | Break2AFMode);
-}
-
-#else
-/**
-  * @brief  Configure the break 2 input.
-  * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance provides a second break input.
-  * @rmtoll BDTR         BK2P          LL_TIM_ConfigBRK2\n
-  *         BDTR         BK2F          LL_TIM_ConfigBRK2
-  * @param  TIMx Timer instance
-  * @param  Break2Polarity This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_BREAK2_POLARITY_LOW
-  *         @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
-  * @param  Break2Filter This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter)
-{
-  MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F, Break2Polarity | Break2Filter);
-}
-
-#endif /*TIM_BDTR_BKBID */
-#if defined(TIM_BDTR_BKBID)
-/**
-  * @brief  Disarm the break 2 input (when it operates in bidirectional mode).
-  * @note  The break 2 input can be disarmed only when it is configured in
-  *        bidirectional mode and when when MOE is reset.
-  * @note  Purpose is to be able to have the input voltage back to high-state,
-  *        whatever the time constant on the output.
-  * @rmtoll BDTR         BK2DSRM       LL_TIM_DisarmBRK2
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
-}
-
-#endif /*TIM_BDTR_BKBID */
-/**
-  * @brief  Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
-  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance provides a break input.
-  * @rmtoll BDTR         OSSI          LL_TIM_SetOffStates\n
-  *         BDTR         OSSR          LL_TIM_SetOffStates
-  * @param  TIMx Timer instance
-  * @param  OffStateIdle This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_OSSI_DISABLE
-  *         @arg @ref LL_TIM_OSSI_ENABLE
-  * @param  OffStateRun This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_OSSR_DISABLE
-  *         @arg @ref LL_TIM_OSSR_ENABLE
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
-{
-  MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
-}
-
-/**
-  * @brief  Enable automatic output (MOE can be set by software or automatically when a break input is active).
-  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance provides a break input.
-  * @rmtoll BDTR         AOE           LL_TIM_EnableAutomaticOutput
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
-}
-
-/**
-  * @brief  Disable automatic output (MOE can be set only by software).
-  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance provides a break input.
-  * @rmtoll BDTR         AOE           LL_TIM_DisableAutomaticOutput
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
-}
-
-/**
-  * @brief  Indicate whether automatic output is enabled.
-  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance provides a break input.
-  * @rmtoll BDTR         AOE           LL_TIM_IsEnabledAutomaticOutput
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable the outputs (set the MOE bit in TIMx_BDTR register).
-  * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
-  *       software and is reset in case of break or break2 event
-  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance provides a break input.
-  * @rmtoll BDTR         MOE           LL_TIM_EnableAllOutputs
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
-}
-
-/**
-  * @brief  Disable the outputs (reset the MOE bit in TIMx_BDTR register).
-  * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
-  *       software and is reset in case of break or break2 event.
-  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance provides a break input.
-  * @rmtoll BDTR         MOE           LL_TIM_DisableAllOutputs
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
-}
-
-/**
-  * @brief  Indicates whether outputs are enabled.
-  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance provides a break input.
-  * @rmtoll BDTR         MOE           LL_TIM_IsEnabledAllOutputs
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
-}
-
-#if defined(TIM_BREAK_INPUT_SUPPORT)
-/**
-  * @brief  Enable the signals connected to the designated timer break input.
-  * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
-  *       or not a timer instance allows for break input selection.
-  * @rmtoll AF1          BKINE         LL_TIM_EnableBreakInputSource\n
-  *         AF1          BKCMP1E       LL_TIM_EnableBreakInputSource\n
-  *         AF1          BKCMP2E       LL_TIM_EnableBreakInputSource\n
-  *         AF1          BKDF1BK0E     LL_TIM_EnableBreakInputSource\n
-  *         AF2          BK2INE        LL_TIM_EnableBreakInputSource\n
-  *         AF2          BK2CMP1E      LL_TIM_EnableBreakInputSource\n
-  *         AF2          BK2CMP2E      LL_TIM_EnableBreakInputSource\n
-  *         AF2          BK2DF1BK1E    LL_TIM_EnableBreakInputSource
-  * @param  TIMx Timer instance
-  * @param  BreakInput This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN
-  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN2
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_BKIN_SOURCE_BKIN
-  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
-  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
-  *         @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
-{
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
-  SET_BIT(*pReg, Source);
-}
-
-/**
-  * @brief  Disable the signals connected to the designated timer break input.
-  * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
-  *       or not a timer instance allows for break input selection.
-  * @rmtoll AF1          BKINE         LL_TIM_DisableBreakInputSource\n
-  *         AF1          BKCMP1E       LL_TIM_DisableBreakInputSource\n
-  *         AF1          BKCMP2E       LL_TIM_DisableBreakInputSource\n
-  *         AF1          BKDF1BK0E     LL_TIM_DisableBreakInputSource\n
-  *         AF2          BK2INE        LL_TIM_DisableBreakInputSource\n
-  *         AF2          BK2CMP1E      LL_TIM_DisableBreakInputSource\n
-  *         AF2          BK2CMP2E      LL_TIM_DisableBreakInputSource\n
-  *         AF2          BK2DF1BK1E    LL_TIM_DisableBreakInputSource
-  * @param  TIMx Timer instance
-  * @param  BreakInput This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN
-  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN2
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_BKIN_SOURCE_BKIN
-  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
-  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
-  *         @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
-{
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
-  CLEAR_BIT(*pReg, Source);
-}
-
-/**
-  * @brief  Set the polarity of the break signal for the timer break input.
-  * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
-  *       or not a timer instance allows for break input selection.
-  * @rmtoll AF1          BKINP         LL_TIM_SetBreakInputSourcePolarity\n
-  *         AF1          BKCMP1P       LL_TIM_SetBreakInputSourcePolarity\n
-  *         AF1          BKCMP2P       LL_TIM_SetBreakInputSourcePolarity\n
-  *         AF2          BK2INP        LL_TIM_SetBreakInputSourcePolarity\n
-  *         AF2          BK2CMP1P      LL_TIM_SetBreakInputSourcePolarity\n
-  *         AF2          BK2CMP2P      LL_TIM_SetBreakInputSourcePolarity
-  * @param  TIMx Timer instance
-  * @param  BreakInput This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN
-  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN2
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_BKIN_SOURCE_BKIN
-  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
-  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
-  * @param  Polarity This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_BKIN_POLARITY_LOW
-  *         @arg @ref LL_TIM_BKIN_POLARITY_HIGH
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
-                                                        uint32_t Polarity)
-{
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
-  MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE));
-}
-#endif /* TIM_BREAK_INPUT_SUPPORT */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
-  * @{
-  */
-/**
-  * @brief  Configures the timer DMA burst feature.
-  * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
-  *       not a timer instance supports the DMA burst mode.
-  * @rmtoll DCR          DBL           LL_TIM_ConfigDMABurst\n
-  *         DCR          DBA           LL_TIM_ConfigDMABurst
-  * @param  TIMx Timer instance
-  * @param  DMABurstBaseAddress This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_SR
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_AF1
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_AF2
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_TISEL
-  *
-  * @param  DMABurstLength This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
-{
-  MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
-  * @{
-  */
-/**
-  * @brief  Remap TIM inputs (input channel, internal/external triggers).
-  * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
-  *       a some timer inputs can be remapped.
-  *         TIM1: one of the following values:
-  *            @arg LL_TIM_TIM1_TI1_RMP_GPIO:                TIM1 TI1 is connected to GPIO
-  *            @arg LL_TIM_TIM1_TI1_RMP_COMP1:               TIM1 TI1 is connected to COMP1 output
-  *
-  *         TIM2: one of the following values:
-  *            @arg LL_TIM_TIM2_TI4_RMP_GPIO:                TIM2 TI4 is connected to GPIO
-  *            @arg LL_TIM_TIM2_TI4_RMP_COMP1:               TIM2 TI4 is connected to COMP1 output
-  *            @arg LL_TIM_TIM2_TI4_RMP_COMP2:               TIM2 TI4 is connected to COMP2 output
-  *            @arg LL_TIM_TIM2_TI4_RMP_COMP1_COMP2:         TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output
-  *
-  *         TIM3: one of the following values:
-  *            @arg LL_TIM_TIM3_TI1_RMP_GPIO:                TIM3 TI1 is connected to GPIO
-  *            @arg LL_TIM_TIM3_TI1_RMP_COMP1:               TIM3 TI1 is connected to COMP1 output
-  *            @arg LL_TIM_TIM3_TI1_RMP_COMP2:               TIM3 TI1 is connected to COMP2 output
-  *            @arg LL_TIM_TIM3_TI1_RMP_COMP1_COMP2:         TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output
-  *
-  *         TIM5: one of the following values:
-  *            @arg LL_TIM_TIM5_TI1_RMP_GPIO:                TIM5 TI1 is connected to GPIO
-  *            @arg LL_TIM_TIM5_TI1_RMP_CAN_TMP:             TIM5 TI1 is connected to CAN TMP
-  *            @arg LL_TIM_TIM5_TI1_RMP_CAN_RTP:             TIM5 TI1 is connected to CAN RTP
-  *
-  *         TIM8: one of the following values:
-  *            @arg LL_TIM_TIM8_TI1_RMP_GPIO:               TIM8 TI1 is connected to GPIO
-  *            @arg LL_TIM_TIM8_TI1_RMP_COMP2:              TIM8 TI1 is connected to COMP2 output
-  *
-  *         TIM12: one of the following values: (*)
-  *            @arg LL_TIM_TIM12_TI1_RMP_GPIO:              TIM12 TI1 is connected to GPIO
-  *            @arg LL_TIM_TIM12_TI1_RMP_SPDIF_FS:          TIM12 TI1 is connected to SPDIF FS
-  *
-  *         TIM15: one of the following values:
-  *            @arg LL_TIM_TIM15_TI1_RMP_GPIO:              TIM15 TI1 is connected to GPIO
-  *            @arg LL_TIM_TIM15_TI1_RMP_TIM2:              TIM15 TI1 is connected to TIM2 CH1
-  *            @arg LL_TIM_TIM15_TI1_RMP_TIM3:              TIM15 TI1 is connected to TIM3 CH1
-  *            @arg LL_TIM_TIM15_TI1_RMP_TIM4:              TIM15 TI1 is connected to TIM4 CH1
-  *            @arg LL_TIM_TIM15_TI1_RMP_LSE:               TIM15 TI1 is connected to LSE
-  *            @arg LL_TIM_TIM15_TI1_RMP_CSI:               TIM15 TI1 is connected to CSI
-  *            @arg LL_TIM_TIM15_TI1_RMP_MCO2:              TIM15 TI1 is connected to MCO2
-  *            @arg LL_TIM_TIM15_TI2_RMP_GPIO:              TIM15 TI2 is connected to GPIO
-  *            @arg LL_TIM_TIM15_TI2_RMP_TIM2:              TIM15 TI2 is connected to TIM2 CH2
-  *            @arg LL_TIM_TIM15_TI2_RMP_TIM3:              TIM15 TI2 is connected to TIM3 CH2
-  *            @arg LL_TIM_TIM15_TI2_RMP_TIM4:              TIM15 TI2 is connected to TIM4 CH2
-  *
-  *         TIM16: one of the following values:
-  *            @arg LL_TIM_TIM16_TI1_RMP_GPIO:              TIM16 TI1 is connected to GPIO
-  *            @arg LL_TIM_TIM16_TI1_RMP_LSI:               TIM16 TI1 is connected to LSI
-  *            @arg LL_TIM_TIM16_TI1_RMP_LSE:               TIM16 TI1 is connected to LSE
-  *            @arg LL_TIM_TIM16_TI1_RMP_RTC:               TIM16 TI1 is connected to RTC wakeup interrupt
-  *
-  *         TIM17: one of the following values:
-  *            @arg LL_TIM_TIM17_TI1_RMP_GPIO:              TIM17 TI1 is connected to GPIO
-  *            @arg LL_TIM_TIM17_TI1_RMP_SPDIF_FS:          TIM17 TI1 is connected to SPDIF FS (*)
-  *            @arg LL_TIM_TIM17_TI1_RMP_HSE_1MHZ:          TIM17 TI1 is connected to HSE 1MHz
-  *            @arg LL_TIM_TIM17_TI1_RMP_MCO1:              TIM17 TI1 is connected to MCO1
-  *
-  *         TIM23: one of the following values: (*)
-  *            @arg LL_TIM_TIM23_TI4_RMP_GPIO               TIM23_TI4 is connected to GPIO
-  *            @arg LL_TIM_TIM23_TI4_RMP_COMP1              TIM23_TI4 is connected to COMP1 output
-  *            @arg LL_TIM_TIM23_TI4_RMP_COMP2              TIM23_TI4 is connected to COMP2 output
-  *            @arg LL_TIM_TIM23_TI4_RMP_COMP1_COMP2        TIM23_TI4 is connected to COMP2 output
-  *
-  *         TIM24: one of the following values: (*)
-  *            @arg LL_TIM_TIM24_TI1_RMP_GPIO               TIM24_TI1 is connected to GPIO
-  *            @arg LL_TIM_TIM24_TI1_RMP_CAN_TMP            TIM24_TI1 is connected to CAN_TMP
-  *            @arg LL_TIM_TIM24_TI1_RMP_CAN_RTP            TIM24_TI1 is connected to CAN_RTP
-  *            @arg LL_TIM_TIM24_TI1_RMP_CAN_SOC            TIM24_TI1 is connected to CAN_SOC
-  *
-  *         (*)  Value not defined in all devices. \n
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
-{
-  MODIFY_REG(TIMx->TISEL, (TIM_TISEL_TI1SEL | TIM_TISEL_TI2SEL | TIM_TISEL_TI3SEL | TIM_TISEL_TI4SEL), Remap);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
-  * @{
-  */
-/**
-  * @brief  Clear the update interrupt flag (UIF).
-  * @rmtoll SR           UIF           LL_TIM_ClearFlag_UPDATE
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
-}
-
-/**
-  * @brief  Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
-  * @rmtoll SR           UIF           LL_TIM_IsActiveFlag_UPDATE
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear the Capture/Compare 1 interrupt flag (CC1F).
-  * @rmtoll SR           CC1IF         LL_TIM_ClearFlag_CC1
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
-}
-
-/**
-  * @brief  Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
-  * @rmtoll SR           CC1IF         LL_TIM_IsActiveFlag_CC1
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear the Capture/Compare 2 interrupt flag (CC2F).
-  * @rmtoll SR           CC2IF         LL_TIM_ClearFlag_CC2
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
-}
-
-/**
-  * @brief  Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
-  * @rmtoll SR           CC2IF         LL_TIM_IsActiveFlag_CC2
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear the Capture/Compare 3 interrupt flag (CC3F).
-  * @rmtoll SR           CC3IF         LL_TIM_ClearFlag_CC3
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
-}
-
-/**
-  * @brief  Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
-  * @rmtoll SR           CC3IF         LL_TIM_IsActiveFlag_CC3
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear the Capture/Compare 4 interrupt flag (CC4F).
-  * @rmtoll SR           CC4IF         LL_TIM_ClearFlag_CC4
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
-}
-
-/**
-  * @brief  Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
-  * @rmtoll SR           CC4IF         LL_TIM_IsActiveFlag_CC4
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear the Capture/Compare 5 interrupt flag (CC5F).
-  * @rmtoll SR           CC5IF         LL_TIM_ClearFlag_CC5
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
-}
-
-/**
-  * @brief  Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
-  * @rmtoll SR           CC5IF         LL_TIM_IsActiveFlag_CC5
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear the Capture/Compare 6 interrupt flag (CC6F).
-  * @rmtoll SR           CC6IF         LL_TIM_ClearFlag_CC6
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
-}
-
-/**
-  * @brief  Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
-  * @rmtoll SR           CC6IF         LL_TIM_IsActiveFlag_CC6
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear the commutation interrupt flag (COMIF).
-  * @rmtoll SR           COMIF         LL_TIM_ClearFlag_COM
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
-}
-
-/**
-  * @brief  Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
-  * @rmtoll SR           COMIF         LL_TIM_IsActiveFlag_COM
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear the trigger interrupt flag (TIF).
-  * @rmtoll SR           TIF           LL_TIM_ClearFlag_TRIG
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
-}
-
-/**
-  * @brief  Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
-  * @rmtoll SR           TIF           LL_TIM_IsActiveFlag_TRIG
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear the break interrupt flag (BIF).
-  * @rmtoll SR           BIF           LL_TIM_ClearFlag_BRK
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
-}
-
-/**
-  * @brief  Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
-  * @rmtoll SR           BIF           LL_TIM_IsActiveFlag_BRK
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear the break 2 interrupt flag (B2IF).
-  * @rmtoll SR           B2IF          LL_TIM_ClearFlag_BRK2
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
-}
-
-/**
-  * @brief  Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
-  * @rmtoll SR           B2IF          LL_TIM_IsActiveFlag_BRK2
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
-  * @rmtoll SR           CC1OF         LL_TIM_ClearFlag_CC1OVR
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
-}
-
-/**
-  * @brief  Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set
-  *         (Capture/Compare 1 interrupt is pending).
-  * @rmtoll SR           CC1OF         LL_TIM_IsActiveFlag_CC1OVR
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
-  * @rmtoll SR           CC2OF         LL_TIM_ClearFlag_CC2OVR
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
-}
-
-/**
-  * @brief  Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set
-  *         (Capture/Compare 2 over-capture interrupt is pending).
-  * @rmtoll SR           CC2OF         LL_TIM_IsActiveFlag_CC2OVR
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
-  * @rmtoll SR           CC3OF         LL_TIM_ClearFlag_CC3OVR
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
-}
-
-/**
-  * @brief  Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set
-  *         (Capture/Compare 3 over-capture interrupt is pending).
-  * @rmtoll SR           CC3OF         LL_TIM_IsActiveFlag_CC3OVR
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
-  * @rmtoll SR           CC4OF         LL_TIM_ClearFlag_CC4OVR
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
-}
-
-/**
-  * @brief  Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set
-  *         (Capture/Compare 4 over-capture interrupt is pending).
-  * @rmtoll SR           CC4OF         LL_TIM_IsActiveFlag_CC4OVR
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear the system break interrupt flag (SBIF).
-  * @rmtoll SR           SBIF          LL_TIM_ClearFlag_SYSBRK
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));
-}
-
-/**
-  * @brief  Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
-  * @rmtoll SR           SBIF          LL_TIM_IsActiveFlag_SYSBRK
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EF_IT_Management IT-Management
-  * @{
-  */
-/**
-  * @brief  Enable update interrupt (UIE).
-  * @rmtoll DIER         UIE           LL_TIM_EnableIT_UPDATE
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_UIE);
-}
-
-/**
-  * @brief  Disable update interrupt (UIE).
-  * @rmtoll DIER         UIE           LL_TIM_DisableIT_UPDATE
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
-}
-
-/**
-  * @brief  Indicates whether the update interrupt (UIE) is enabled.
-  * @rmtoll DIER         UIE           LL_TIM_IsEnabledIT_UPDATE
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable capture/compare 1 interrupt (CC1IE).
-  * @rmtoll DIER         CC1IE         LL_TIM_EnableIT_CC1
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
-}
-
-/**
-  * @brief  Disable capture/compare 1  interrupt (CC1IE).
-  * @rmtoll DIER         CC1IE         LL_TIM_DisableIT_CC1
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
-}
-
-/**
-  * @brief  Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
-  * @rmtoll DIER         CC1IE         LL_TIM_IsEnabledIT_CC1
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable capture/compare 2 interrupt (CC2IE).
-  * @rmtoll DIER         CC2IE         LL_TIM_EnableIT_CC2
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
-}
-
-/**
-  * @brief  Disable capture/compare 2  interrupt (CC2IE).
-  * @rmtoll DIER         CC2IE         LL_TIM_DisableIT_CC2
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
-}
-
-/**
-  * @brief  Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
-  * @rmtoll DIER         CC2IE         LL_TIM_IsEnabledIT_CC2
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable capture/compare 3 interrupt (CC3IE).
-  * @rmtoll DIER         CC3IE         LL_TIM_EnableIT_CC3
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
-}
-
-/**
-  * @brief  Disable capture/compare 3  interrupt (CC3IE).
-  * @rmtoll DIER         CC3IE         LL_TIM_DisableIT_CC3
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
-}
-
-/**
-  * @brief  Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
-  * @rmtoll DIER         CC3IE         LL_TIM_IsEnabledIT_CC3
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable capture/compare 4 interrupt (CC4IE).
-  * @rmtoll DIER         CC4IE         LL_TIM_EnableIT_CC4
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
-}
-
-/**
-  * @brief  Disable capture/compare 4  interrupt (CC4IE).
-  * @rmtoll DIER         CC4IE         LL_TIM_DisableIT_CC4
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
-}
-
-/**
-  * @brief  Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
-  * @rmtoll DIER         CC4IE         LL_TIM_IsEnabledIT_CC4
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable commutation interrupt (COMIE).
-  * @rmtoll DIER         COMIE         LL_TIM_EnableIT_COM
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
-}
-
-/**
-  * @brief  Disable commutation interrupt (COMIE).
-  * @rmtoll DIER         COMIE         LL_TIM_DisableIT_COM
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
-}
-
-/**
-  * @brief  Indicates whether the commutation interrupt (COMIE) is enabled.
-  * @rmtoll DIER         COMIE         LL_TIM_IsEnabledIT_COM
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable trigger interrupt (TIE).
-  * @rmtoll DIER         TIE           LL_TIM_EnableIT_TRIG
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_TIE);
-}
-
-/**
-  * @brief  Disable trigger interrupt (TIE).
-  * @rmtoll DIER         TIE           LL_TIM_DisableIT_TRIG
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
-}
-
-/**
-  * @brief  Indicates whether the trigger interrupt (TIE) is enabled.
-  * @rmtoll DIER         TIE           LL_TIM_IsEnabledIT_TRIG
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable break interrupt (BIE).
-  * @rmtoll DIER         BIE           LL_TIM_EnableIT_BRK
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_BIE);
-}
-
-/**
-  * @brief  Disable break interrupt (BIE).
-  * @rmtoll DIER         BIE           LL_TIM_DisableIT_BRK
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
-}
-
-/**
-  * @brief  Indicates whether the break interrupt (BIE) is enabled.
-  * @rmtoll DIER         BIE           LL_TIM_IsEnabledIT_BRK
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EF_DMA_Management DMA Management
-  * @{
-  */
-/**
-  * @brief  Enable update DMA request (UDE).
-  * @rmtoll DIER         UDE           LL_TIM_EnableDMAReq_UPDATE
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_UDE);
-}
-
-/**
-  * @brief  Disable update DMA request (UDE).
-  * @rmtoll DIER         UDE           LL_TIM_DisableDMAReq_UPDATE
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
-}
-
-/**
-  * @brief  Indicates whether the update DMA request  (UDE) is enabled.
-  * @rmtoll DIER         UDE           LL_TIM_IsEnabledDMAReq_UPDATE
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable capture/compare 1 DMA request (CC1DE).
-  * @rmtoll DIER         CC1DE         LL_TIM_EnableDMAReq_CC1
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
-}
-
-/**
-  * @brief  Disable capture/compare 1  DMA request (CC1DE).
-  * @rmtoll DIER         CC1DE         LL_TIM_DisableDMAReq_CC1
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
-}
-
-/**
-  * @brief  Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
-  * @rmtoll DIER         CC1DE         LL_TIM_IsEnabledDMAReq_CC1
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable capture/compare 2 DMA request (CC2DE).
-  * @rmtoll DIER         CC2DE         LL_TIM_EnableDMAReq_CC2
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
-}
-
-/**
-  * @brief  Disable capture/compare 2  DMA request (CC2DE).
-  * @rmtoll DIER         CC2DE         LL_TIM_DisableDMAReq_CC2
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
-}
-
-/**
-  * @brief  Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
-  * @rmtoll DIER         CC2DE         LL_TIM_IsEnabledDMAReq_CC2
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable capture/compare 3 DMA request (CC3DE).
-  * @rmtoll DIER         CC3DE         LL_TIM_EnableDMAReq_CC3
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
-}
-
-/**
-  * @brief  Disable capture/compare 3  DMA request (CC3DE).
-  * @rmtoll DIER         CC3DE         LL_TIM_DisableDMAReq_CC3
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
-}
-
-/**
-  * @brief  Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
-  * @rmtoll DIER         CC3DE         LL_TIM_IsEnabledDMAReq_CC3
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable capture/compare 4 DMA request (CC4DE).
-  * @rmtoll DIER         CC4DE         LL_TIM_EnableDMAReq_CC4
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
-}
-
-/**
-  * @brief  Disable capture/compare 4  DMA request (CC4DE).
-  * @rmtoll DIER         CC4DE         LL_TIM_DisableDMAReq_CC4
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
-}
-
-/**
-  * @brief  Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
-  * @rmtoll DIER         CC4DE         LL_TIM_IsEnabledDMAReq_CC4
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable commutation DMA request (COMDE).
-  * @rmtoll DIER         COMDE         LL_TIM_EnableDMAReq_COM
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
-}
-
-/**
-  * @brief  Disable commutation DMA request (COMDE).
-  * @rmtoll DIER         COMDE         LL_TIM_DisableDMAReq_COM
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
-}
-
-/**
-  * @brief  Indicates whether the commutation DMA request (COMDE) is enabled.
-  * @rmtoll DIER         COMDE         LL_TIM_IsEnabledDMAReq_COM
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable trigger interrupt (TDE).
-  * @rmtoll DIER         TDE           LL_TIM_EnableDMAReq_TRIG
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_TDE);
-}
-
-/**
-  * @brief  Disable trigger interrupt (TDE).
-  * @rmtoll DIER         TDE           LL_TIM_DisableDMAReq_TRIG
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
-}
-
-/**
-  * @brief  Indicates whether the trigger interrupt (TDE) is enabled.
-  * @rmtoll DIER         TDE           LL_TIM_IsEnabledDMAReq_TRIG
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
-  * @{
-  */
-/**
-  * @brief  Generate an update event.
-  * @rmtoll EGR          UG            LL_TIM_GenerateEvent_UPDATE
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->EGR, TIM_EGR_UG);
-}
-
-/**
-  * @brief  Generate Capture/Compare 1 event.
-  * @rmtoll EGR          CC1G          LL_TIM_GenerateEvent_CC1
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
-}
-
-/**
-  * @brief  Generate Capture/Compare 2 event.
-  * @rmtoll EGR          CC2G          LL_TIM_GenerateEvent_CC2
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
-}
-
-/**
-  * @brief  Generate Capture/Compare 3 event.
-  * @rmtoll EGR          CC3G          LL_TIM_GenerateEvent_CC3
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
-}
-
-/**
-  * @brief  Generate Capture/Compare 4 event.
-  * @rmtoll EGR          CC4G          LL_TIM_GenerateEvent_CC4
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
-}
-
-/**
-  * @brief  Generate commutation event.
-  * @rmtoll EGR          COMG          LL_TIM_GenerateEvent_COM
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->EGR, TIM_EGR_COMG);
-}
-
-/**
-  * @brief  Generate trigger event.
-  * @rmtoll EGR          TG            LL_TIM_GenerateEvent_TRIG
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->EGR, TIM_EGR_TG);
-}
-
-/**
-  * @brief  Generate break event.
-  * @rmtoll EGR          BG            LL_TIM_GenerateEvent_BRK
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->EGR, TIM_EGR_BG);
-}
-
-/**
-  * @brief  Generate break 2 event.
-  * @rmtoll EGR          B2G           LL_TIM_GenerateEvent_BRK2
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->EGR, TIM_EGR_B2G);
-}
-
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
-  * @{
-  */
-
-ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx);
-void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
-ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct);
-void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
-ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
-void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
-ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
-void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
-ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
-void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
-ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
-void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
-ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM12 || TIM13 ||TIM14 || TIM15 || TIM16 || TIM17  || TIM23  || TIM24 */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_LL_TIM_H */
diff --git a/fw/User/adv7611.c b/fw/User/adv7611.c
index 4460380..9b94625 100644
--- a/fw/User/adv7611.c
+++ b/fw/User/adv7611.c
@@ -46,18 +46,18 @@ static const uint8_t adv7611_init_1[] = {
     ADV7611_I2C_ADDR,   0x01, 0x06, // Prim_mode = 110b HDMI-GR
     ADV7611_I2C_ADDR,   0x00, 0x16, // VID-STD: UXGA (for default clock)
     ADV7611_I2C_ADDR,   0x02, 0xf2, // F8 = YUV, F2 = RGB
-    ADV7611_I2C_ADDR,   0x03, 0x40, // 40 = 24bit 444 SDR
-    ADV7611_I2C_ADDR,   0x04, 0x46, // P[23:16] V/R, P[15:8] Y/G, P[7:0] U/CrCb/B CLK=24MHz
+    ADV7611_I2C_ADDR,   0x03, 0x60, // 40 = 24bit 444 DDR
+    ADV7611_I2C_ADDR,   0x04, 0x66, // P[23:16] V/R, P[15:8] Y/G, P[7:0] U/CrCb/B CLK=24MHz
     ADV7611_I2C_ADDR,   0x05, 0x28, // Do not insert AV codes
     ADV7611_I2C_ADDR,   0x06, 0xa6, // VS OUT SEL, F/VS/HS/LLC POL
     ADV7611_I2C_ADDR,   0x0b, 0x44,
-    ADV7611_I2C_ADDR,   0x0C, 0x42,
+    ADV7611_I2C_ADDR,   0x0c, 0x42,
     ADV7611_I2C_ADDR,   0x15, 0x80,
-    ADV7611_I2C_ADDR,   0x19, 0x8a, // Enable LLC DLL
+    ADV7611_I2C_ADDR,   0x19, 0x94, // Enable LLC DLL
     ADV7611_I2C_ADDR,   0x33, 0x40,
-    ADV7611_I2C_ADDR,   0x14, 0x7f,
+    ADV7611_I2C_ADDR,   0x14, 0x37, // 37
     CP_I2C_ADDR,        0xba, 0x00, // Disable free run
-    //HDMI_I2C_ADDR,      0xbf, 0x01, // Bypass CP
+    HDMI_I2C_ADDR,      0xbf, 0x01, // Bypass CP
     CP_I2C_ADDR,        0x6c, 0x00, // ADI required setting
     KSV_I2C_ADDR,       0x40, 0x81, // DSP_Ctrl4 :00/01 : YUV or RGB; 10 : RAW8; 11 : RAW10
     HDMI_I2C_ADDR,      0x9b, 0x03, // ADI required setting
@@ -84,7 +84,7 @@ static const uint8_t adv7611_init_1[] = {
     HDMI_I2C_ADDR,      0x57, 0xda, // ADI required setting
     HDMI_I2C_ADDR,      0x58, 0x01, // ADI required setting
     HDMI_I2C_ADDR,      0x03, 0x98, // Set DIS_I2C_ZERO_COMPR 0x03[7]=1
-    HDMI_I2C_ADDR,      0x4c, 0x44, // Set NEW_VS_PARAM 0x44[2]=1
+    HDMI_I2C_ADDR,      0x4c, 0x40, // Set NEW_VS_PARAM 0x44[2]=0
     HDMI_I2C_ADDR,      0x75, 0x10,
 };
 
@@ -131,7 +131,7 @@ uint8_t adv7611_read_reg(uint8_t addr, uint8_t reg) {
     return val;
 }
 
-void adv7611_early_init() {
+void adv7611_early_init(void) {
     // Initialize IO, reset ADV7611 and allocate I2C addresses
     // So it won't conflict with other ICs
     gpio_put(DEC_RST, 1);
@@ -141,7 +141,7 @@ void adv7611_early_init() {
     gpio_put(DEC_RST, 1);
 }
 
-void adv7611_init() {
+void adv7611_init(void) {
     adv7611_send_init_seq(adv7611_init_0, sizeof(adv7611_init_0) / 3);
     adv7611_send_init_seq(adv7611_init_1, sizeof(adv7611_init_1) / 3);
 
@@ -152,3 +152,11 @@ void adv7611_init() {
 
     syslog_printf("ADV7611 initialization done\n");
 }
+
+void adv7611_powerdown(void) {
+    uint8_t buf[2];
+    buf[0] = 0x0c;
+    buf[1] = 0x62; // Power down
+    int result;
+    result = pal_i2c_write_payload(ADV7611_I2C, ADV7611_I2C_ADDR, buf, 2);
+}
diff --git a/fw/User/adv7611.h b/fw/User/adv7611.h
index a57b76d..b414526 100644
--- a/fw/User/adv7611.h
+++ b/fw/User/adv7611.h
@@ -25,3 +25,4 @@
 void adv7611_early_init(void);
 void adv7611_init(void);
 uint8_t adv7611_read_reg(uint8_t addr, uint8_t reg);
+void adv7611_powerdown(void);
diff --git a/fw/User/app_main.c b/fw/User/app_main.c
index 8d2d2cf..e79a02a 100644
--- a/fw/User/app_main.c
+++ b/fw/User/app_main.c
@@ -81,10 +81,8 @@ static portTASK_FUNCTION(startup_task, pvParameters) {
     edid_init();
     adv7611_early_init(); // Must be before PTN3460 to release RST and I2C bus
     ptn3460_early_init(); // Let PTN3460 starts internal bootup process
-    fpga_init();
     adv7611_init();
     ptn3460_init();
-    caster_init(); // must be after adv7611 as it's the clock source for CSR interface
     power_set_vcom(config.vcom); // Move out from here
     power_set_vgh(config.vgh);
     ui_init();
@@ -101,7 +99,7 @@ static portTASK_FUNCTION(startup_task, pvParameters) {
         NULL, UI_TASK_PRIORITY, &ui_task_handle);
     xTaskCreate(key_scan_task, "KeyScanTask", KEY_SCAN_TASK_STACK_SIZE,
         NULL, KEY_SCAN_TASK_PRIORITY, &key_scan_task_handle);
-    xTaskCreate(power_monitor_task, "PowerMonitorTask", POWER_MON_TASK_STACK_SIZE,
+    xTaskCreate(power_monitor_task, "PowerMonTask", POWER_MON_TASK_STACK_SIZE,
         NULL, POWER_MON_TASK_PRIORITY, &power_mon_task_handle);
 
     vTaskPrioritySet(NULL, STARTUP_TASK_LOW_PRIORITY);
diff --git a/fw/User/board.h b/fw/User/board.h
index 7cf4682..50e3637 100644
--- a/fw/User/board.h
+++ b/fw/User/board.h
@@ -70,6 +70,7 @@
 #define FUSB302_I2C_ADDR    (0x22)
 #define INA3221_0_I2C_ADDR  (0x40)
 #define INA3221_1_I2C_ADDR  (0x41)
+#define INA3221_2_I2C_ADDR  (0x42)
 
 // ADV7611 Sub addresses, make sure they don't conflict with anything else!
 #define CEC_I2C_ADDR        (0x3F) // Default 0x40(0x80)
diff --git a/fw/User/config.c b/fw/User/config.c
index 58dfa07..a92ffc6 100644
--- a/fw/User/config.c
+++ b/fw/User/config.c
@@ -28,29 +28,123 @@ config_t config;
 
 void config_init(void) {
     // Set default values
-    config.pclk_hz = 162000000;
-    config.hact = 1600;
-    config.vact = 1200;
-    config.hblk = 560;
-    config.hfp = 64;
-    config.hsync = 192;
-    config.vblk = 50;
-    config.vfp = 1;
-    config.vsync = 3;
     config.size_x_mm = 270;
     config.size_y_mm = 203;
     config.mfg_week = 1;
     config.mfg_year = 0x20;
-    config.tcon_vfp = 45;
+
+    // 1600x1200 @ 60
+//    config.pclk_hz = 162000000;
+//    config.hact = 1600;
+//    config.vact = 1200;
+//    config.hblk = 560;
+//    config.hfp = 64;
+//    config.hsync = 192;
+//    config.vblk = 50;
+//    config.vfp = 1;
+//    config.vsync = 3;
+//    config.tcon_vfp = 45;
+//    config.tcon_vsync = 1;
+//    config.tcon_vbp = 2;
+//    config.tcon_vact = 1200;
+//    config.tcon_hfp = 120;
+//    config.tcon_hsync = 10;
+//    config.tcon_hbp = 10;
+//    config.tcon_hact = 400;
+
+    // 1600x1200 @ 75
+    config.pclk_hz = 156618000;
+    config.hact = 1600;
+    config.vact = 1200;
+    config.hblk = 80;
+    config.hfp = 8;
+    config.hsync = 32;
+    config.vblk = 43;
+    config.vfp = 29;
+    config.vsync = 8;
+
+    config.tcon_vfp = 11;
     config.tcon_vsync = 1;
     config.tcon_vbp = 2;
     config.tcon_vact = 1200;
-    config.tcon_hfp = 120;
-    config.tcon_hsync = 10;
-    config.tcon_hbp = 10;
+    // HFP + HSYNC + HBP = Incoming HBLK / 4
+    config.tcon_hfp = 16;
+    config.tcon_hsync = 2;
+    config.tcon_hbp = 2;
     config.tcon_hact = 400;
-    config.vcom = -2.45f;
-    config.vgh = 22.0f;
+
+
+    // 1448x1072 @ 75
+//    config.pclk_hz = 127320000;
+//    config.hact = 1448;
+//    config.vact = 1072;
+//    config.hblk = 80;
+//    config.hfp = 8;
+//    config.hsync = 32;
+//    config.vblk = 39;
+//    config.vfp = 25;
+//    config.vsync = 8;
+//
+//    config.tcon_vfp = 11;
+//    config.tcon_vsync = 1;
+//    config.tcon_vbp = 2;
+//    config.tcon_vact = 1072;
+//    // HFP + HSYNC + HBP = Incoming HBLK / 4
+//    config.tcon_hfp = 17;
+//    config.tcon_hsync = 2;
+//    config.tcon_hbp = 1;
+//    config.tcon_hact = 362;
+
+//    config.pclk_hz = 72509000;
+//    config.hact = 1040;
+//    config.vact = 1040;
+//    config.hblk = 80;
+//    config.hfp = 8;
+//    config.hsync = 32;
+//    config.vblk = 39;
+//    config.vfp = 25;
+//    config.vsync = 8;
+//
+//    config.tcon_vfp = 11;
+//    config.tcon_vsync = 1;
+//    config.tcon_vbp = 2;
+//    config.tcon_vact = 1040;
+//    // HFP + HSYNC + HBP = Incoming HBLK / 4
+//    config.tcon_hfp = 17;
+//    config.tcon_hsync = 2;
+//    config.tcon_hbp = 1;
+//    config.tcon_hact = 260;
+//
+//    config.vcom = -2.45f;
+//    config.vgh = 22.0f;
+//
+//    config.mirror = 0;
+
+    // 2232x1680 @ 40
+//    config.pclk_hz = 158873000;
+//    config.hact = 2240;
+//    config.vact = 1680;
+//    config.hblk = 80;
+//    config.hfp = 8;
+//    config.hsync = 32;
+//    config.vblk = 32;
+//    config.vfp = 18;
+//    config.vsync = 8;
+//
+//    config.tcon_vfp = 12;
+//    config.tcon_vsync = 1;
+//    config.tcon_vbp = 1;
+//    config.tcon_vact = 1680;
+//    // HFP + HSYNC + HBP = Incoming HBLK / 4
+//    config.tcon_hfp = 16;
+//    config.tcon_hsync = 2;
+//    config.tcon_hbp = 2;
+//    config.tcon_hact = 560;
+//
+//    config.vcom = -0.8f;
+//    config.vgh = 22.0f;
+//
+//    config.mirror = 1;
 }
 
 void config_load(void) {
@@ -78,4 +172,4 @@ void config_save(void) {
         return;
     
     SPIFFS_write(&spiffs_fs, f, &config, sizeof(config));
-}
\ No newline at end of file
+}
diff --git a/fw/User/config.h b/fw/User/config.h
index 8ec371f..ba1cc01 100644
--- a/fw/User/config.h
+++ b/fw/User/config.h
@@ -47,6 +47,7 @@ typedef struct {
     uint8_t tcon_hsync;
     uint8_t tcon_hbp;
     uint16_t tcon_hact;
+    uint8_t mirror;
 } config_t;
 
 extern config_t config;
diff --git a/fw/User/fpga.c b/fw/User/fpga.c
index e0849d1..a4df9ed 100644
--- a/fw/User/fpga.c
+++ b/fw/User/fpga.c
@@ -139,19 +139,23 @@ static void fpga_wait_done(bool timeout) {
     }
 }
 
-void fpga_init(void) {
-    // Initialize FPGA pins
-    gpio_put(FPGA_CS, 1);
-
+void fpga_reset(void) {
     // FPGA Reset
     gpio_put(FPGA_PROG, 0);
     sleep_ms(2);
     gpio_put(FPGA_PROG, 1);
     sleep_ms(10);
+}
+
+void fpga_init(const char *fn) {
+    // Initialize FPGA pins
+    gpio_put(FPGA_CS, 1);
+
+    fpga_reset();
 
     // Load bitstream
 #if 1
-    fpga_load_bitstream("fpga.bit");
+    fpga_load_bitstream(fn);
     fpga_wait_done(true);
 #else
     //fpga_wait_done(false);
diff --git a/fw/User/fpga.h b/fw/User/fpga.h
index 44cc71d..ca1be94 100644
--- a/fw/User/fpga.h
+++ b/fw/User/fpga.h
@@ -22,9 +22,10 @@
 //
 #pragma once
 
-void fpga_init(void);
+void fpga_init(const char *fn);
+void fpga_reset(void);
 void fpga_suspend(void);
 void fpga_resume(void);
 uint8_t fpga_write_reg8(uint8_t addr, uint8_t val);
 void fpga_write_reg16(uint8_t addr, uint16_t val);
-void fpga_write_bulk(uint8_t addr, uint8_t *buf, int length);
\ No newline at end of file
+void fpga_write_bulk(uint8_t addr, uint8_t *buf, int length);
diff --git a/fw/User/power.c b/fw/User/power.c
index 818f138..73b74c1 100644
--- a/fw/User/power.c
+++ b/fw/User/power.c
@@ -24,6 +24,15 @@
 #include "board.h"
 #include "app.h"
 
+static bool adc_conv_done;
+static uint16_t adc_buffer[6];
+
+static float voltages[14];
+static float currents[8];
+static float p_cur[8];
+static float p_avg[8];
+static float p_max[8];
+
 void power_on(void) {
 
 }
@@ -89,20 +98,132 @@ void power_set_vgh(float vgh) {
 }
 
 void power_on_fl(void) {
-	HAL_TIM_PWM_Start(&htim1, TIM_CHANNEL_3);
+	//HAL_TIM_PWM_Start(&htim1, TIM_CHANNEL_3);
 }
 
 void power_off_fl(void) {
-	HAL_TIM_PWM_Stop(&htim1, TIM_CHANNEL_3);
+	//HAL_TIM_PWM_Stop(&htim1, TIM_CHANNEL_3);
 }
 
 void power_set_fl_brightness(uint8_t val) {
-	TIM1->CCR3 = 255 - val;
+	//TIM1->CCR3 = 255 - val;
+}
+
+static void ina_write(uint8_t addr, uint8_t reg, uint16_t val) {
+    uint8_t buf[2] = {val & 0xff, val >> 8};
+    int result = pal_i2c_write_longreg(INA3221_I2C, addr, reg, buf, 2);
+    if (result != 0) {
+        syslog_printf("Failed writing data to INA3221\n");
+    }
+}
+
+static uint16_t ina_read(uint8_t addr, uint8_t reg) {
+    uint8_t buf[2];
+    int result = pal_i2c_read_payload(INA3221_I2C, addr, &reg, 1, buf, 2);
+    if (result != 0) {
+        syslog_printf("Failed reading data from INA3221\n");
+    }
+    return ((uint16_t)buf[0] << 8) | buf[1];
+}
+
+static void power_ina_init(uint8_t addr) {
+    syslog_printf("INA %02x: Mfg ID = %04x, Die ID = %04x\n", addr, ina_read(addr, 0xfe), ina_read(addr, 0xff));
+}
+
+float power_get_rail_voltage(power_rail_t rail) {
+    return voltages[(int)rail];
+}
+
+float power_get_rail_current(power_rail_t rail) {
+    int ch = (int)rail;
+    if (ch > 8)
+        return 0.0f;
+    return currents[ch];
+}
+
+void power_get_rail_power(power_rail_t rail, float *cur, float *avg, float *max) {
+    *cur = p_cur[(int)rail];
+    *avg = p_avg[(int)rail];
+    *max = p_max[(int)rail];
+}
+
+// No internal reference, ref_voltage is the full level (65535) voltage / VDDA voltage
+static float convert_positive_adc_voltage(uint16_t sample, float ref_voltage) {
+    return (float)sample / 65535.0f * ref_voltage * 11.0f;
+}
+
+static float convert_negative_adc_voltage(uint16_t sample, float ref_voltage) {
+    return convert_positive_adc_voltage(sample, ref_voltage) - ref_voltage * 10.f;
+}
+
+static float convert_bus_voltage(uint16_t sample) {
+    return (float)(*(int16_t *)&sample) / 1000.f;
+}
+
+static float convert_shunt_current(uint16_t sample) {
+    float shunt_mv = (float)(*(int16_t *)&sample) / 200.f;
+    float shunt_ma = shunt_mv / 0.02f;
+    return shunt_ma;
+}
+
+void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc) {
+    adc_conv_done = true;
+    HAL_ADC_Stop_DMA(hadc);
 }
 
 portTASK_FUNCTION(power_monitor_task, pvParameters) {
-    power_on_epd();
+    HAL_StatusTypeDef result = HAL_ADCEx_Calibration_Start(&hadc1, ADC_CALIB_OFFSET_LINEARITY, ADC_SINGLE_ENDED);
+    if (result != HAL_OK) {
+        syslog_printf("ADC failed to calibrate\n");
+    }
+    power_ina_init(INA3221_0_I2C_ADDR);
+    power_ina_init(INA3221_1_I2C_ADDR);
+    power_ina_init(INA3221_2_I2C_ADDR);
+    adc_conv_done = true;
+    const uint8_t ina_shunt_regs[] = {
+        // I2C ADDR, REG NUM
+        INA3221_0_I2C_ADDR, 0x01,
+        INA3221_0_I2C_ADDR, 0x03,
+        INA3221_0_I2C_ADDR, 0x05,
+        INA3221_1_I2C_ADDR, 0x01,
+        INA3221_1_I2C_ADDR, 0x03,
+        INA3221_1_I2C_ADDR, 0x05,
+        INA3221_2_I2C_ADDR, 0x01,
+        INA3221_2_I2C_ADDR, 0x03,
+    };
+    const uint8_t ina_bus_regs[] = {
+        // I2C ADDR, REG NUM
+        INA3221_0_I2C_ADDR, 0x02,
+        INA3221_0_I2C_ADDR, 0x04,
+        INA3221_0_I2C_ADDR, 0x06,
+        INA3221_1_I2C_ADDR, 0x02,
+        INA3221_1_I2C_ADDR, 0x04,
+        INA3221_1_I2C_ADDR, 0x06,
+        INA3221_2_I2C_ADDR, 0x02,
+        INA3221_2_I2C_ADDR, 0x04,
+    };
     while (1) {
+        for (int i = 0; i < 8; i++) {
+            currents[i] = convert_shunt_current(ina_read(ina_shunt_regs[i * 2], ina_shunt_regs[i * 2 + 1]));
+            voltages[i] = convert_bus_voltage(ina_read(ina_bus_regs[i * 2], ina_bus_regs[i * 2 + 1]));
+        }
+        if (adc_conv_done == true) {
+            // Update numbers
+            for (int i = 0; i < 3; i++) {
+                voltages[8 + i] = convert_positive_adc_voltage(adc_buffer[i], voltages[RAIL_3V3]);
+            }
+            for (int i = 3; i < 6; i++) {
+                voltages[8 + i] = convert_negative_adc_voltage(adc_buffer[i], voltages[RAIL_3V3]);
+            }
+            adc_conv_done = false;
+            HAL_ADC_Start_DMA(&hadc1, (uint32_t *)adc_buffer, 6);
+        }
+        // Update values
+        for (int i = 0; i < 8; i++) {
+            p_cur[i] = voltages[i] * currents[i];
+            p_avg[i] = p_avg[i] * 0.9f + p_cur[i] * 0.1f;
+            if (p_cur[i] > p_max[i]) p_max[i] = p_cur[i];
+        }
         vTaskDelay(pdMS_TO_TICKS(100)); // Nothing for now
     }
 }
diff --git a/fw/User/power.h b/fw/User/power.h
index e4b9b7a..99936b2 100644
--- a/fw/User/power.h
+++ b/fw/User/power.h
@@ -22,6 +22,25 @@
 //
 #pragma once
 
+typedef enum {
+    // Rails with both voltage and current monitoring
+    RAIL_5VES,
+    RAIL_5VEG,
+    RAIL_3V3,
+    RAIL_1V8VID,
+    RAIL_3V3VID,
+    RAIL_5V2FL,
+    RAIL_1V35,
+    RAIL_1V2,
+    // Rails with only voltage monitoring
+    RAIL_VP,
+    RAIL_VGH,
+    RAIL_VBUS,
+    RAIL_VCOM,
+    RAIL_VN,
+    RAIL_VGL,
+} power_rail_t;
+
 void power_off(void);
 void power_on(void);
 void power_on_epd(void);
@@ -31,4 +50,7 @@ void power_set_vgh(float vgh);
 void power_on_fl(void);
 void power_off_fl(void);
 void power_set_fl_brightness(uint8_t val);
+float power_get_rail_voltage(power_rail_t rail);
+float power_get_rail_current(power_rail_t rail);
+void power_get_rail_power(power_rail_t rail, float *cur, float *avg, float *max);
 portTASK_FUNCTION(power_monitor_task, pvParameters);
diff --git a/fw/User/ptn3460.c b/fw/User/ptn3460.c
index 74f497c..2c77d7d 100644
--- a/fw/User/ptn3460.c
+++ b/fw/User/ptn3460.c
@@ -82,3 +82,7 @@ void ptn3460_set_aux_polarity(int reverse) {
     else
         ptn3460_write(0x80, 0x00); // Disable AUX reverse
 }
+
+void ptn3460_powerdown(void) {
+    gpio_put(DP_PDN, 0);
+}
diff --git a/fw/User/shell/shell.c b/fw/User/shell/shell.c
index de8b87c..77e7491 100644
--- a/fw/User/shell/shell.c
+++ b/fw/User/shell/shell.c
@@ -67,30 +67,32 @@ typedef struct
 SHELL_FUNC( shell_help );
 SHELL_FUNC( shell_ver );
 SHELL_FUNC( shell_syslog );
+SHELL_FUNC( shell_stacks );
 SHELL_FUNC( shell_test );
 SHELL_FUNC( shell_i2c_probe );
-SHELL_FUNC( shell_fl );
 SHELL_FUNC( shell_recv );
 SHELL_FUNC( shell_send );
 SHELL_FUNC( shell_df );
-SHELL_FUNC( shell_dump );
-SHELL_FUNC( shell_fdump );
+SHELL_FUNC( shell_format );
+SHELL_FUNC( shell_rm );
 SHELL_FUNC( shell_setvolt );
 SHELL_FUNC( shell_setcfg );
+SHELL_FUNC( shell_sensor );
 
 SHELL_HELP( help );
 SHELL_HELP( ver );
 SHELL_HELP( syslog );
+SHELL_HELP( stacks );
 SHELL_HELP( test );
 SHELL_HELP( i2c_probe );
-SHELL_HELP( fl );
 SHELL_HELP( recv );
 SHELL_HELP( send );
 SHELL_HELP( df );
-SHELL_HELP( dump );
-SHELL_HELP( fdump );
+SHELL_HELP( format );
+SHELL_HELP( rm );
 SHELL_HELP( setvolt );
 SHELL_HELP( setcfg );
+SHELL_HELP( sensor );
 
 //static const SHELL_COMMAND shell_commands[] =
 const SHELL_COMMAND shell_commands[] =
@@ -98,16 +100,17 @@ const SHELL_COMMAND shell_commands[] =
   { "help", shell_help },
   { "ver", shell_ver },
   { "syslog", shell_syslog },
+  { "stacks", shell_stacks },
   { "test", shell_test },
   { "i2c_probe", shell_i2c_probe },
-  { "fl", shell_fl },
   { "recv", shell_recv },
   { "send", shell_send },
   { "df", shell_df },
-  { "dump", shell_dump },
-  { "fdump", shell_fdump },
+  { "format", shell_format },
+  { "rm", shell_rm },
   { "setvolt", shell_setvolt },
   { "setcfg", shell_setcfg },
+  { "sensor", shell_sensor },
   { "exit", NULL },
   { NULL, NULL }
 };
@@ -117,16 +120,17 @@ static const SHELL_HELP_DATA shell_help_data[] =
   SHELL_INFO( help ),
   SHELL_INFO( ver ),
   SHELL_INFO( syslog ),
+  SHELL_INFO( stacks ),
   SHELL_INFO( test ),
   SHELL_INFO( i2c_probe ),
-  SHELL_INFO( fl ),
   SHELL_INFO( recv ),
   SHELL_INFO( send ),
   SHELL_INFO( df ),
-  SHELL_INFO( dump ),
-  SHELL_INFO( fdump ),
+  SHELL_INFO( format ),
+  SHELL_INFO( rm ),
   SHELL_INFO( setvolt ),
   SHELL_INFO( setcfg ),
+  SHELL_INFO( sensor ),
   { NULL, NULL, NULL }
 };
 
diff --git a/fw/User/shell/shell_cmds.c b/fw/User/shell/shell_cmds.c
index cc5df90..1d32df7 100644
--- a/fw/User/shell/shell_cmds.c
+++ b/fw/User/shell/shell_cmds.c
@@ -146,56 +146,62 @@ const char shell_help_summary_test[] = "Test command";
 
 void shell_test(shell_context_t *ctx, int argc, char **argv ) {
 
-    uint8_t val;
+//    uint8_t val = atoi(argv[1]);
+//    uint8_t buf[2];
+//    buf[0] = 0x19;
+//    buf[1] = val | 0x80;
+//     pal_i2c_write_payload(ADV7611_I2C, ADV7611_I2C_ADDR, buf, 2);
 
-    val = adv7611_read_reg(ADV7611_I2C_ADDR, 0x6a);
-    if (val & 0x10)
-        printf("TMDS clock detected\n");
-    else
-        printf("No TMDS clock detected\n");
-
-    uint16_t val16;
-    val = adv7611_read_reg(HDMI_I2C_ADDR, 0x51); // D8-D1
-    val16 = (uint16_t)val << 1;
-    val = adv7611_read_reg(HDMI_I2C_ADDR, 0x52);
-    val16 |= val >> 7;
-
-    printf("TMDS frequency %d MHz\n", val16);
-
-    val = adv7611_read_reg(HDMI_I2C_ADDR, 0x04);
-    if (val & 0x2)
-        printf("TMDS PLL locked\n");
-    else
-        printf("TMDS PLL not locked\n");
-
-    val = adv7611_read_reg(HDMI_I2C_ADDR, 0x05);
-    if (val & 0x80)
-        printf("HDMI mode detected\n");
-    else
-        printf("DVI mode detected\n");
-
-    val = adv7611_read_reg(HDMI_I2C_ADDR, 0x07);
-    if (val & 0x20)
-        printf("DE regeneration locked\n");
-    else
-        printf("DE regeneration not locked\n");
-
-    if (val & 0x80)
-        printf("Vertical filter locked\n");
-    else
-        printf("Vertical filter not locked\n");
-
-    val16 = (uint16_t)adv7611_read_reg(HDMI_I2C_ADDR, 0x1e) << 8;
-    val16 |= adv7611_read_reg(HDMI_I2C_ADDR, 0x1f);
-    printf("Total line width: %d\n", val16);
-
-    val16 = (uint16_t)(adv7611_read_reg(HDMI_I2C_ADDR, 0x07) & 0x1f) << 8;
-    val16 |= adv7611_read_reg(HDMI_I2C_ADDR, 0x08);
-    printf("Active line width: %d\n", val16);
-
-    val16 = (uint16_t)(adv7611_read_reg(HDMI_I2C_ADDR, 0x09) & 0x1f) << 8;
-    val16 |= adv7611_read_reg(HDMI_I2C_ADDR, 0x0a);
-    printf("Active field height: %d\n", val16);
+//    uint8_t val;
+//
+//    val = adv7611_read_reg(ADV7611_I2C_ADDR, 0x6a);
+//    if (val & 0x10)
+//        printf("TMDS clock detected\n");
+//    else
+//        printf("No TMDS clock detected\n");
+//
+//    uint16_t val16;
+//    val = adv7611_read_reg(HDMI_I2C_ADDR, 0x51); // D8-D1
+//    val16 = (uint16_t)val << 1;
+//    val = adv7611_read_reg(HDMI_I2C_ADDR, 0x52);
+//    val16 |= val >> 7;
+//
+//    printf("TMDS frequency %d MHz\n", val16);
+//
+//    val = adv7611_read_reg(HDMI_I2C_ADDR, 0x04);
+//    if (val & 0x2)
+//        printf("TMDS PLL locked\n");
+//    else
+//        printf("TMDS PLL not locked\n");
+//
+//    val = adv7611_read_reg(HDMI_I2C_ADDR, 0x05);
+//    if (val & 0x80)
+//        printf("HDMI mode detected\n");
+//    else
+//        printf("DVI mode detected\n");
+//
+//    val = adv7611_read_reg(HDMI_I2C_ADDR, 0x07);
+//    if (val & 0x20)
+//        printf("DE regeneration locked\n");
+//    else
+//        printf("DE regeneration not locked\n");
+//
+//    if (val & 0x80)
+//        printf("Vertical filter locked\n");
+//    else
+//        printf("Vertical filter not locked\n");
+//
+//    val16 = (uint16_t)adv7611_read_reg(HDMI_I2C_ADDR, 0x1e) << 8;
+//    val16 |= adv7611_read_reg(HDMI_I2C_ADDR, 0x1f);
+//    printf("Total line width: %d\n", val16);
+//
+//    val16 = (uint16_t)(adv7611_read_reg(HDMI_I2C_ADDR, 0x07) & 0x1f) << 8;
+//    val16 |= adv7611_read_reg(HDMI_I2C_ADDR, 0x08);
+//    printf("Active line width: %d\n", val16);
+//
+//    val16 = (uint16_t)(adv7611_read_reg(HDMI_I2C_ADDR, 0x09) & 0x1f) << 8;
+//    val16 |= adv7611_read_reg(HDMI_I2C_ADDR, 0x0a);
+//    printf("Active field height: %d\n", val16);
 }
 
 /***********************************************************************
@@ -236,30 +242,30 @@ void shell_i2c_probe(shell_context_t *ctx, int argc, char **argv)
 }
 
 
-const char shell_help_fl[] = "<operation> [brightness]\n"
-  "  operation - on | off | set\n"
-  "  brightness - 0-255\n";
-const char shell_help_summary_fl[] = "Control front light";
-
-void shell_fl(shell_context_t *ctx, int argc, char **argv)
-{
-    if ((argc < 2) || (argc > 3)) {
-        printf("Invalid arguments. Type help [<command>] for usage.\n");
-        return;
-    }
-
-    if (strcmp(argv[1], "on") == 0) {
-    	power_on_fl();
-    }
-    else if (strcmp(argv[1], "off") == 0) {
-    	power_off_fl();
-    }
-
-    if (argc == 3) {
-    	int brightness = strtol(argv[2], NULL, 0);
-    	power_set_fl_brightness(brightness);
-    }
-}
+//const char shell_help_fl[] = "<operation> [brightness]\n"
+//  "  operation - on | off | set\n"
+//  "  brightness - 0-255\n";
+//const char shell_help_summary_fl[] = "Control front light";
+//
+//void shell_fl(shell_context_t *ctx, int argc, char **argv)
+//{
+//    if ((argc < 2) || (argc > 3)) {
+//        printf("Invalid arguments. Type help [<command>] for usage.\n");
+//        return;
+//    }
+//
+//    if (strcmp(argv[1], "on") == 0) {
+//    	power_on_fl();
+//    }
+//    else if (strcmp(argv[1], "off") == 0) {
+//    	power_off_fl();
+//    }
+//
+//    if (argc == 3) {
+//    	int brightness = strtol(argv[2], NULL, 0);
+//    	power_set_fl_brightness(brightness);
+//    }
+//}
 
 
 /***********************************************************************
@@ -334,97 +340,131 @@ static void file_data_read(void *usr, void *data, int size) {
 }
 
 /***********************************************************************
- * CMD: dump
+ * CMD: format
  **********************************************************************/
-const char shell_help_dump[] = "[addr] <len>\n"
-    "  addr - Starting address to dump\n"
-    "  len - Number of bytes to dump (default 1)\n";
-const char shell_help_summary_dump[] = "Hex dump of flash contents";
+const char shell_help_format[] = "";
+const char shell_help_summary_format[] = "Formats an internal flash filesystem";
 
-void shell_dump(shell_context_t *ctx, int argc, char **argv)
-{
-    uintptr_t addr = 0;
-    unsigned len = 1;
-    uint8_t *buf;
-    int ok;
+void shell_format(shell_context_t *ctx, int argc, char **argv) {
+    printf("Be patient, this may take a while.\n");
+    printf("Formatting...\n");
 
-    if (argc < 2) {
-        printf("Invalid arguments\n");
-        return;
+    if (SPIFFS_format(&spiffs_fs) != SPIFFS_OK) {
+        printf("SPIFFS format failed: %d\n", SPIFFS_errno(&spiffs_fs));
     }
 
-    addr = strtoul(argv[1], NULL, 0);
-    if (argc > 2) {
-        len = strtoul(argv[2], NULL, 0);
-    }
-
-    buf = SHELL_MALLOC(len);
-    if (buf) {
-        ok = spif_read(addr, len, buf);
-        if (ok == 0) {
-            dump_bytes(ctx, buf, addr, len);
-        }
-        SHELL_FREE(buf);
-    }
+    printf("Done.\n");
 }
 
 /***********************************************************************
- * CMD: fdump
+ * CMD: rm/del
  **********************************************************************/
-const char shell_help_fdump[] =
-  "[file] <start> <size>\n"
-  "  file - File to dump\n"
-  "  start - Start offset in bytes (default: 0)\n"
-  "  size - Size in bytes (default: full file)\n";
-const char shell_help_summary_fdump[] = "Dumps the contents of a file in hex";
+const char shell_help_rm[] = "<file1> [<file2> ...]\n";
+const char shell_help_summary_rm[] = "Removes a file";
 
-#define DUMP_SIZE 512
+#include <stdio.h>
 
-void shell_fdump(shell_context_t *ctx, int argc, char **argv) {
-    spiffs_file f;
-    size_t start = 0;
-    size_t size = SIZE_MAX;
-    uint8_t *buf = NULL;
-    size_t rlen;
-    int c;
+void shell_rm(shell_context_t *ctx, int argc, char **argv) {
+    int i;
 
-    if( argc < 2 ) {
-        printf("No file given\n");
+    if (argc < 2) {
+        printf( "Usage: rm <file1> [<file2> ...]\n" );
         return;
     }
 
-    if (argc > 2) {
-        start = (size_t)strtoul(argv[2], NULL, 0);
-    }
-
-    if (argc > 3) {
-        size = (size_t)strtoul(argv[3], NULL, 0);
-    }
-
-    f = SPIFFS_open(&spiffs_fs, argv[1], SPIFFS_O_RDONLY, 0);
-    if (f) {
-        buf = SHELL_MALLOC(DUMP_SIZE);
-        SPIFFS_lseek(&spiffs_fs, f, start, SPIFFS_SEEK_SET);
-        do {
-            rlen = (size < DUMP_SIZE) ? size : DUMP_SIZE;
-            rlen = SPIFFS_read(&spiffs_fs, f, buf, rlen);
-            if (rlen) {
-                dump_bytes(ctx, buf, start, rlen);
-                size -= rlen;
-                start += rlen;
-                c = term_getch(&ctx->t, TERM_INPUT_DONT_WAIT);
-            }
-        } while (size && rlen && (c < 0));
-        if (buf) {
-            SHELL_FREE(buf);
+    for (i = 1; i < argc; i++) {
+        if (SPIFFS_remove(&spiffs_fs, argv[i]) != 0) {
+          printf("Unable to remove '%s'\n", argv[i]);
         }
-        SPIFFS_close(&spiffs_fs, f);
-    }
-    else {
-        printf("Unable to open '%s'\n", argv[1]);
     }
 }
 
+//const char shell_help_dump[] = "[addr] <len>\n"
+//    "  addr - Starting address to dump\n"
+//    "  len - Number of bytes to dump (default 1)\n";
+//const char shell_help_summary_dump[] = "Hex dump of flash contents";
+//
+//void shell_dump(shell_context_t *ctx, int argc, char **argv)
+//{
+//    uintptr_t addr = 0;
+//    unsigned len = 1;
+//    uint8_t *buf;
+//    int ok;
+//
+//    if (argc < 2) {
+//        printf("Invalid arguments\n");
+//        return;
+//    }
+//
+//    addr = strtoul(argv[1], NULL, 0);
+//    if (argc > 2) {
+//        len = strtoul(argv[2], NULL, 0);
+//    }
+//
+//    buf = SHELL_MALLOC(len);
+//    if (buf) {
+//        ok = spif_read(addr, len, buf);
+//        if (ok == 0) {
+//            dump_bytes(ctx, buf, addr, len);
+//        }
+//        SHELL_FREE(buf);
+//    }
+//}
+//
+//const char shell_help_fdump[] =
+//  "[file] <start> <size>\n"
+//  "  file - File to dump\n"
+//  "  start - Start offset in bytes (default: 0)\n"
+//  "  size - Size in bytes (default: full file)\n";
+//const char shell_help_summary_fdump[] = "Dumps the contents of a file in hex";
+//
+//#define DUMP_SIZE 512
+//
+//void shell_fdump(shell_context_t *ctx, int argc, char **argv) {
+//    spiffs_file f;
+//    size_t start = 0;
+//    size_t size = SIZE_MAX;
+//    uint8_t *buf = NULL;
+//    size_t rlen;
+//    int c;
+//
+//    if( argc < 2 ) {
+//        printf("No file given\n");
+//        return;
+//    }
+//
+//    if (argc > 2) {
+//        start = (size_t)strtoul(argv[2], NULL, 0);
+//    }
+//
+//    if (argc > 3) {
+//        size = (size_t)strtoul(argv[3], NULL, 0);
+//    }
+//
+//    f = SPIFFS_open(&spiffs_fs, argv[1], SPIFFS_O_RDONLY, 0);
+//    if (f) {
+//        buf = SHELL_MALLOC(DUMP_SIZE);
+//        SPIFFS_lseek(&spiffs_fs, f, start, SPIFFS_SEEK_SET);
+//        do {
+//            rlen = (size < DUMP_SIZE) ? size : DUMP_SIZE;
+//            rlen = SPIFFS_read(&spiffs_fs, f, buf, rlen);
+//            if (rlen) {
+//                dump_bytes(ctx, buf, start, rlen);
+//                size -= rlen;
+//                start += rlen;
+//                c = term_getch(&ctx->t, TERM_INPUT_DONT_WAIT);
+//            }
+//        } while (size && rlen && (c < 0));
+//        if (buf) {
+//            SHELL_FREE(buf);
+//        }
+//        SPIFFS_close(&spiffs_fs, f);
+//    }
+//    else {
+//        printf("Unable to open '%s'\n", argv[1]);
+//    }
+//}
+
 /***********************************************************************
  * CMD: recv
  **********************************************************************/
@@ -571,107 +611,85 @@ void shell_setvolt(shell_context_t *ctx, int argc, char **argv) {
 const char shell_help_setcfg[] = "<set|get|save> [key] [value]\n";
 const char shell_help_summary_setcfg[] = "Sets configuration. Remember to use save to save it to the flash.";
 
+typedef struct {
+    const char *name;
+    void *pointer;
+    enum {UINT8, UINT16, UINT32, FLOAT32} type;
+} cfg_var_t;
+
+cfg_var_t vars[] = {
+    {"pclk_hz", &(config.pclk_hz), UINT32},
+    {"hfp", &(config.hfp), UINT8},
+    {"vfp", &(config.vfp), UINT8},
+    {"hsync", &(config.hsync), UINT8},
+    {"vsync", &(config.vsync), UINT8},
+    {"hact", &(config.hact), UINT16},
+    {"hblk", &(config.hblk), UINT16},
+    {"vact", &(config.vact), UINT16},
+    {"vblk", &(config.vblk), UINT16},
+    {"size_x_mm", &(config.size_x_mm), UINT16},
+    {"size_y_mm", &(config.size_y_mm), UINT16},
+    {"mfg_week", &(config.mfg_week), UINT8},
+    {"mfg_year", &(config.mfg_year), UINT8},
+    {"vcom", &(config.vcom), FLOAT32},
+    {"vgh", &(config.vgh), FLOAT32},
+    {"tcon_vfp", &(config.tcon_vfp), UINT8},
+    {"tcon_vsync", &(config.tcon_vsync), UINT8},
+    {"tcon_vbp", &(config.tcon_vbp), UINT8},
+    {"tcon_vact", &(config.tcon_vact), UINT16},
+    {"tcon_hfp", &(config.tcon_hfp), UINT8},
+    {"tcon_hsync", &(config.tcon_hsync), UINT8},
+    {"tcon_hbp", &(config.tcon_hbp), UINT8},
+    {"tcon_hact", &(config.tcon_hact), UINT16},
+};
+int num_vars = sizeof(vars) / sizeof(cfg_var_t);
+
+static void setcfg_set_helper(cfg_var_t *var, char *val) {
+    if (var->type == UINT8) {
+        *(uint8_t *)(var->pointer) = strtol(val, NULL, 10);
+    }
+    else if (var->type == UINT16) {
+        *(uint16_t *)(var->pointer) = strtol(val, NULL, 10);
+    }
+    else if (var->type == UINT32) {
+        *(uint32_t *)(var->pointer) = strtol(val, NULL, 10);
+    }
+    else if (var->type == FLOAT32) {
+        *(float *)(var->pointer) = strtof(val, NULL);
+    }
+}
+
+static void setcfg_get_helper(shell_context_t *ctx, cfg_var_t *var) {
+    if (var->type == UINT8) {
+        printf("%d\n", *(uint8_t *)(var->pointer));
+    }
+    else if (var->type == UINT16) {
+        printf("%d\n", *(uint16_t *)(var->pointer));
+    }
+    else if (var->type == UINT32) {
+        printf("%d\n", *(uint32_t *)(var->pointer));
+    }
+    else if (var->type == FLOAT32) {
+        printf("%f\n", *(float *)(var->pointer));
+    }
+}
+
 void shell_setcfg(shell_context_t *ctx, int argc, char **argv) {
     if (argc < 2) {
         printf("Usage: %s\n", shell_help_setcfg);
         return;
     }
 
-    enum {UINT8, UINT16, UINT32, FLOAT32} var_type;
-    void * var_pointer;
+    cfg_var_t *var = NULL;
     if (argc >= 3) {
-        // has key specifier
-        if (strcmp(argv[2], "pclk_hz") == 0) {
-            var_pointer = &(config.pclk_hz);
-            var_type = UINT32;
+        for (int i = 0; i < num_vars; i++) {
+            if (strcmp(argv[2], vars[i].name) == 0) {
+                var = &vars[i];
+            }
         }
-        else if (strcmp(argv[2], "hfp") == 0) {
-            var_pointer = &(config.hfp);
-            var_type = UINT8;
-        }
-        else if (strcmp(argv[2], "vfp") == 0) {
-            var_pointer = &(config.vfp);
-            var_type = UINT8;
-        }
-        else if (strcmp(argv[2], "hsync") == 0) {
-            var_pointer = &(config.hsync);
-            var_type = UINT8;
-        }
-        else if (strcmp(argv[2], "vsync") == 0) {
-            var_pointer = &(config.vsync);
-            var_type = UINT8;
-        }
-        else if (strcmp(argv[2], "hact") == 0) {
-            var_pointer = &(config.hact);
-            var_type = UINT16;
-        }
-        else if (strcmp(argv[2], "hblk") == 0) {
-            var_pointer = &(config.hblk);
-            var_type = UINT16;
-        }
-        else if (strcmp(argv[2], "vact") == 0) {
-            var_pointer = &(config.vact);
-            var_type = UINT16;
-        }
-        else if (strcmp(argv[2], "vblk") == 0) {
-            var_pointer = &(config.vblk);
-            var_type = UINT16;
-        }
-        else if (strcmp(argv[2], "size_x_mm") == 0) {
-            var_pointer = &(config.size_x_mm);
-            var_type = UINT16;
-        }
-        else if (strcmp(argv[2], "size_y_mm") == 0) {
-            var_pointer = &(config.size_y_mm);
-            var_type = UINT16;
-        }
-        else if (strcmp(argv[2], "mfg_week") == 0) {
-            var_pointer = &(config.mfg_week);
-            var_type = UINT8;
-        }
-        else if (strcmp(argv[2], "mfg_year") == 0) {
-            var_pointer = &(config.mfg_year);
-            var_type = UINT8;
-        }
-        else if (strcmp(argv[2], "vcom") == 0) {
-            var_pointer = &(config.vcom);
-            var_type = FLOAT32;
-        }
-        else if (strcmp(argv[2], "vgh") == 0) {
-            var_pointer = &(config.vgh);
-            var_type = FLOAT32;
-        }
-        else if (strcmp(argv[2], "tcon_vfp") == 0) {
-            var_pointer = &(config.tcon_vfp);
-            var_type = UINT8;
-        }
-        else if (strcmp(argv[2], "tcon_vsync") == 0) {
-            var_pointer = &(config.tcon_vsync);
-            var_type = UINT8;
-        }
-        else if (strcmp(argv[2], "tcon_vbp") == 0) {
-            var_pointer = &(config.tcon_vbp);
-            var_type = UINT8;
-        }
-        else if (strcmp(argv[2], "tcon_vact") == 0) {
-            var_pointer = &(config.tcon_vact);
-            var_type = UINT16;
-        }
-        else if (strcmp(argv[2], "tcon_hfp") == 0) {
-            var_pointer = &(config.tcon_hfp);
-            var_type = UINT8;
-        }
-        else if (strcmp(argv[2], "tcon_hsync") == 0) {
-            var_pointer = &(config.tcon_hsync);
-            var_type = UINT8;
-        }
-        else if (strcmp(argv[2], "tcon_hbp") == 0) {
-            var_pointer = &(config.tcon_hbp);
-            var_type = UINT8;
-        }
-        else if (strcmp(argv[2], "tcon_hact") == 0) {
-            var_pointer = &(config.tcon_hact);
-            var_type = UINT16;
+        if (var == NULL) {
+            printf("Unknown key %s", argv[2]);
+            return;
         }
     }
 
@@ -680,34 +698,63 @@ void shell_setcfg(shell_context_t *ctx, int argc, char **argv) {
             printf("Key and value required for set\n");
             return;
         }
-        if (var_type == UINT8) {
-            *(uint8_t *)var_pointer = strtol(argv[3], NULL, 10);
-        }
-        else if (var_type == UINT16) {
-            *(uint16_t *)var_pointer = strtol(argv[3], NULL, 10);
-        }
-        else if (var_type == UINT32) {
-            *(uint32_t *)var_pointer = strtol(argv[3], NULL, 10);
-        }
-        else if (var_type == FLOAT32) {
-            *(float *)var_pointer = strtof(argv[3], NULL);
-        }
+        setcfg_set_helper(var, argv[3]);
     }
     else if (strcmp(argv[1], "get") == 0) {
-        if (var_type == UINT8) {
-            printf("%d\n", *(uint8_t *)var_pointer);
+        if (argc < 4) {
+            // Get every var
+            for (int i = 0; i < num_vars; i++) {
+                printf("%s: ", vars[i].name);
+                setcfg_get_helper(ctx, &vars[i]);
+            }
         }
-        else if (var_type == UINT16) {
-            printf("%d\n", *(uint16_t *)var_pointer);
-        }
-        else if (var_type == UINT32) {
-            printf("%d\n", *(uint32_t *)var_pointer);
-        }
-        else if (var_type == FLOAT32) {
-            printf("%f\n", *(float *)var_pointer);
+        else {
+            setcfg_get_helper(ctx, var);
         }
     }
     else if (strcmp(argv[1], "save") == 0) {
         config_save();
     }
 }
+
+const char shell_help_sensor[] = "\n";
+const char shell_help_summary_sensor[] = "Get sensor readings";
+
+void shell_sensor(shell_context_t *ctx, int argc, char **argv) {
+    printf("EPD Supplies:\n");
+    printf("VP:     %5.2f V\n", power_get_rail_voltage(RAIL_VP));
+    printf("VGH:    %5.2f V\n", power_get_rail_voltage(RAIL_VGH));
+    printf("VN:     %5.2f V\n", power_get_rail_voltage(RAIL_VN));
+    printf("VGL:    %5.2f V\n", power_get_rail_voltage(RAIL_VGL));
+    printf("VCOM:   %5.2f V\n", power_get_rail_voltage(RAIL_VCOM));
+    printf("5VES:   %5.2f V %3.0f mA\n", power_get_rail_voltage(RAIL_5VES), power_get_rail_current(RAIL_5VES));
+    printf("5VEG:   %5.2f V %3.0f mA\n", power_get_rail_voltage(RAIL_5VEG), power_get_rail_current(RAIL_5VEG));
+
+    printf("System Supplies:\n");
+    printf("VBUS:   %5.2f V\n", power_get_rail_voltage(RAIL_VBUS));
+    printf("3V3:    %5.2f V %3.0f mA\n", power_get_rail_voltage(RAIL_3V3), power_get_rail_current(RAIL_3V3));
+    printf("1V8VID: %5.2f V %3.0f mA\n", power_get_rail_voltage(RAIL_1V8VID), power_get_rail_current(RAIL_1V8VID));
+    printf("3V3VID: %5.2f V %3.0f mA\n", power_get_rail_voltage(RAIL_3V3VID), power_get_rail_current(RAIL_3V3VID));
+    printf("5V2FL:  %5.2f V %3.0f mA\n", power_get_rail_voltage(RAIL_5V2FL), power_get_rail_current(RAIL_5V2FL));
+    printf("1V35:   %5.2f V %3.0f mA\n", power_get_rail_voltage(RAIL_1V35), power_get_rail_current(RAIL_1V35));
+    printf("1V2:    %5.2f V %3.0f mA\n", power_get_rail_voltage(RAIL_1V2), power_get_rail_current(RAIL_1V2));
+
+    float p_cur, p_avg, p_max;
+    float p_cur_sum, p_avg_sum, p_max_sum;
+
+    printf("Power Consumption (CUR, AVG, MAX):\n");
+    power_get_rail_power(RAIL_3V3, &p_cur, &p_avg, &p_max);
+    printf("MCU + IO:  %5.1f mW  %5.1f mW  %5.1f mW\n", p_cur, p_avg, p_max);
+    power_get_rail_power(RAIL_1V35, &p_cur, &p_avg, &p_max);
+    printf("FPGA DDR:  %5.1f mW  %5.1f mW  %5.1f mW\n", p_cur, p_avg, p_max);
+    power_get_rail_power(RAIL_1V2, &p_cur, &p_avg, &p_max);
+    printf("FPGA CORE: %5.1f mW  %5.1f mW  %5.1f mW\n", p_cur, p_avg, p_max);
+    power_get_rail_power(RAIL_1V8VID, &p_cur_sum, &p_avg_sum, &p_max_sum);
+    power_get_rail_power(RAIL_3V3VID, &p_cur, &p_avg, &p_max);
+    p_cur_sum += p_cur; p_avg_sum += p_avg; p_max_sum += p_max;
+    printf("VIDEO IN:  %5.1f mW  %5.1f mW  %5.1f mW\n", p_cur_sum, p_avg_sum, p_max_sum);
+    power_get_rail_power(RAIL_5VES, &p_cur_sum, &p_avg_sum, &p_max_sum);
+    power_get_rail_power(RAIL_5VEG, &p_cur, &p_avg, &p_max);
+    p_cur_sum += p_cur; p_avg_sum += p_avg; p_max_sum += p_max;
+    printf("EPD HV:    %5.1f mW  %5.1f mW  %5.1f mW\n", p_cur_sum, p_avg_sum, p_max_sum);
+}
diff --git a/fw/User/usbapp.c b/fw/User/usbapp.c
index 5e1cdac..88a0238 100644
--- a/fw/User/usbapp.c
+++ b/fw/User/usbapp.c
@@ -112,10 +112,10 @@ void tud_hid_set_report_cb(uint8_t instance, uint8_t report_id, hid_report_type_
         // TODO
         break;
     case USBCMD_REDRAW:
-        //retval = caster_redraw(x0, y0, x1, y1);
+        retval = caster_redraw(x0, y0, x1, y1);
         break;
     case USBCMD_SETMODE:
-        //retval = caster_setmode(x0, y0, x1, y1, (UPDATE_MODE)param);
+        retval = caster_setmode(x0, y0, x1, y1, (update_mode_t)param);
         break;
     case USBCMD_USBBOOT:
         //iap_usbboot();
diff --git a/fw/glider_ec_rtos.ioc b/fw/glider_ec_rtos.ioc
index 1f2ee09..22c06e2 100644
--- a/fw/glider_ec_rtos.ioc
+++ b/fw/glider_ec_rtos.ioc
@@ -1,11 +1,40 @@
 #MicroXplorer Configuration settings - do not modify
-ADC1.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_7
-ADC1.IPParameters=Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,OffsetNumber-0\#ChannelRegularConversion,OffsetSignedSaturation-0\#ChannelRegularConversion,NbrOfConversionFlag,master
+ADC1.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_3
+ADC1.Channel-1\#ChannelRegularConversion=ADC_CHANNEL_4
+ADC1.Channel-2\#ChannelRegularConversion=ADC_CHANNEL_5
+ADC1.Channel-3\#ChannelRegularConversion=ADC_CHANNEL_7
+ADC1.Channel-4\#ChannelRegularConversion=ADC_CHANNEL_8
+ADC1.Channel-5\#ChannelRegularConversion=ADC_CHANNEL_9
+ADC1.ConversionDataManagement=ADC_CONVERSIONDATA_DMA_ONESHOT
+ADC1.IPParameters=Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,OffsetNumber-0\#ChannelRegularConversion,OffsetSignedSaturation-0\#ChannelRegularConversion,NbrOfConversionFlag,master,ConversionDataManagement,Rank-1\#ChannelRegularConversion,Channel-1\#ChannelRegularConversion,SamplingTime-1\#ChannelRegularConversion,OffsetNumber-1\#ChannelRegularConversion,OffsetSignedSaturation-1\#ChannelRegularConversion,Rank-2\#ChannelRegularConversion,Channel-2\#ChannelRegularConversion,SamplingTime-2\#ChannelRegularConversion,OffsetNumber-2\#ChannelRegularConversion,OffsetSignedSaturation-2\#ChannelRegularConversion,Rank-3\#ChannelRegularConversion,Channel-3\#ChannelRegularConversion,SamplingTime-3\#ChannelRegularConversion,OffsetNumber-3\#ChannelRegularConversion,OffsetSignedSaturation-3\#ChannelRegularConversion,Rank-4\#ChannelRegularConversion,Channel-4\#ChannelRegularConversion,SamplingTime-4\#ChannelRegularConversion,OffsetNumber-4\#ChannelRegularConversion,OffsetSignedSaturation-4\#ChannelRegularConversion,Rank-5\#ChannelRegularConversion,Channel-5\#ChannelRegularConversion,SamplingTime-5\#ChannelRegularConversion,OffsetNumber-5\#ChannelRegularConversion,OffsetSignedSaturation-5\#ChannelRegularConversion,NbrOfConversion,OversamplingMode,Ratio
+ADC1.NbrOfConversion=6
 ADC1.NbrOfConversionFlag=1
 ADC1.OffsetNumber-0\#ChannelRegularConversion=ADC_OFFSET_NONE
+ADC1.OffsetNumber-1\#ChannelRegularConversion=ADC_OFFSET_NONE
+ADC1.OffsetNumber-2\#ChannelRegularConversion=ADC_OFFSET_NONE
+ADC1.OffsetNumber-3\#ChannelRegularConversion=ADC_OFFSET_NONE
+ADC1.OffsetNumber-4\#ChannelRegularConversion=ADC_OFFSET_NONE
+ADC1.OffsetNumber-5\#ChannelRegularConversion=ADC_OFFSET_NONE
 ADC1.OffsetSignedSaturation-0\#ChannelRegularConversion=DISABLE
+ADC1.OffsetSignedSaturation-1\#ChannelRegularConversion=DISABLE
+ADC1.OffsetSignedSaturation-2\#ChannelRegularConversion=DISABLE
+ADC1.OffsetSignedSaturation-3\#ChannelRegularConversion=DISABLE
+ADC1.OffsetSignedSaturation-4\#ChannelRegularConversion=DISABLE
+ADC1.OffsetSignedSaturation-5\#ChannelRegularConversion=DISABLE
+ADC1.OversamplingMode=DISABLE
 ADC1.Rank-0\#ChannelRegularConversion=1
+ADC1.Rank-1\#ChannelRegularConversion=2
+ADC1.Rank-2\#ChannelRegularConversion=3
+ADC1.Rank-3\#ChannelRegularConversion=4
+ADC1.Rank-4\#ChannelRegularConversion=5
+ADC1.Rank-5\#ChannelRegularConversion=6
+ADC1.Ratio=1
 ADC1.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_1CYCLE_5
+ADC1.SamplingTime-1\#ChannelRegularConversion=ADC_SAMPLETIME_1CYCLE_5
+ADC1.SamplingTime-2\#ChannelRegularConversion=ADC_SAMPLETIME_1CYCLE_5
+ADC1.SamplingTime-3\#ChannelRegularConversion=ADC_SAMPLETIME_1CYCLE_5
+ADC1.SamplingTime-4\#ChannelRegularConversion=ADC_SAMPLETIME_1CYCLE_5
+ADC1.SamplingTime-5\#ChannelRegularConversion=ADC_SAMPLETIME_1CYCLE_5
 ADC1.master=1
 CAD.formats=[]
 CAD.pinconfig=Dual
@@ -15,8 +44,27 @@ CORTEX_M7.default_mode_Activation=1
 DAC1.DAC_Channel-DAC_OUT1=DAC_CHANNEL_1
 DAC1.DAC_Channel-DAC_OUT2=DAC_CHANNEL_2
 DAC1.IPParameters=DAC_Channel-DAC_OUT1,DAC_Channel-DAC_OUT2
+Dma.ADC1.1.Direction=DMA_PERIPH_TO_MEMORY
+Dma.ADC1.1.EventEnable=DISABLE
+Dma.ADC1.1.FIFOMode=DMA_FIFOMODE_DISABLE
+Dma.ADC1.1.Instance=DMA1_Stream1
+Dma.ADC1.1.MemDataAlignment=DMA_MDATAALIGN_HALFWORD
+Dma.ADC1.1.MemInc=DMA_MINC_ENABLE
+Dma.ADC1.1.Mode=DMA_NORMAL
+Dma.ADC1.1.PeriphDataAlignment=DMA_PDATAALIGN_HALFWORD
+Dma.ADC1.1.PeriphInc=DMA_PINC_DISABLE
+Dma.ADC1.1.Polarity=HAL_DMAMUX_REQ_GEN_RISING
+Dma.ADC1.1.Priority=DMA_PRIORITY_LOW
+Dma.ADC1.1.RequestNumber=1
+Dma.ADC1.1.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
+Dma.ADC1.1.SignalID=NONE
+Dma.ADC1.1.SyncEnable=DISABLE
+Dma.ADC1.1.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
+Dma.ADC1.1.SyncRequestNumber=1
+Dma.ADC1.1.SyncSignalID=NONE
 Dma.Request0=SPI2_TX
-Dma.RequestsNb=1
+Dma.Request1=ADC1
+Dma.RequestsNb=2
 Dma.SPI2_TX.0.Direction=DMA_MEMORY_TO_PERIPH
 Dma.SPI2_TX.0.EventEnable=DISABLE
 Dma.SPI2_TX.0.FIFOMode=DMA_FIFOMODE_DISABLE
@@ -108,8 +156,7 @@ Mcu.IP12=RCC
 Mcu.IP13=SDMMC2
 Mcu.IP14=SPI2
 Mcu.IP15=SYS
-Mcu.IP16=TIM1
-Mcu.IP17=USB_OTG_FS
+Mcu.IP16=USB_OTG_FS
 Mcu.IP2=DAC1
 Mcu.IP3=DEBUG
 Mcu.IP4=DMA
@@ -118,33 +165,33 @@ Mcu.IP6=FREERTOS
 Mcu.IP7=I2C1
 Mcu.IP8=MDMA
 Mcu.IP9=MEMORYMAP
-Mcu.IPNb=18
+Mcu.IPNb=17
 Mcu.Name=STM32H750VBTx
 Mcu.Package=LQFP100
 Mcu.Pin0=PE2
-Mcu.Pin1=PC14-OSC32_IN (OSC32_IN)
-Mcu.Pin10=PA2
-Mcu.Pin11=PA3
-Mcu.Pin12=PA4
-Mcu.Pin13=PA5
-Mcu.Pin14=PA6
-Mcu.Pin15=PA7
-Mcu.Pin16=PC4
-Mcu.Pin17=PC5
-Mcu.Pin18=PB0
-Mcu.Pin19=PB1
-Mcu.Pin2=PC15-OSC32_OUT (OSC32_OUT)
-Mcu.Pin20=PB2
-Mcu.Pin21=PE7
-Mcu.Pin22=PE8
-Mcu.Pin23=PE9
-Mcu.Pin24=PE10
-Mcu.Pin25=PE11
-Mcu.Pin26=PE12
-Mcu.Pin27=PE13
-Mcu.Pin28=PE14
+Mcu.Pin1=PE3
+Mcu.Pin10=PA0
+Mcu.Pin11=PA1
+Mcu.Pin12=PA2
+Mcu.Pin13=PA3
+Mcu.Pin14=PA4
+Mcu.Pin15=PA5
+Mcu.Pin16=PA6
+Mcu.Pin17=PA7
+Mcu.Pin18=PC4
+Mcu.Pin19=PC5
+Mcu.Pin2=PE4
+Mcu.Pin20=PB0
+Mcu.Pin21=PB1
+Mcu.Pin22=PB2
+Mcu.Pin23=PE7
+Mcu.Pin24=PE8
+Mcu.Pin25=PE9
+Mcu.Pin26=PE10
+Mcu.Pin27=PE11
+Mcu.Pin28=PE12
 Mcu.Pin29=PE15
-Mcu.Pin3=PH0-OSC_IN (PH0)
+Mcu.Pin3=PC14-OSC32_IN (OSC32_IN)
 Mcu.Pin30=PB10
 Mcu.Pin31=PB12
 Mcu.Pin32=PB13
@@ -155,7 +202,7 @@ Mcu.Pin36=PD12
 Mcu.Pin37=PD14
 Mcu.Pin38=PD15
 Mcu.Pin39=PC7
-Mcu.Pin4=PH1-OSC_OUT (PH1)
+Mcu.Pin4=PC15-OSC32_OUT (OSC32_OUT)
 Mcu.Pin40=PC9
 Mcu.Pin41=PA10
 Mcu.Pin42=PA11
@@ -166,7 +213,7 @@ Mcu.Pin46=PA15 (JTDI)
 Mcu.Pin47=PC10
 Mcu.Pin48=PC11
 Mcu.Pin49=PC12
-Mcu.Pin5=PC1
+Mcu.Pin5=PH0-OSC_IN (PH0)
 Mcu.Pin50=PD0
 Mcu.Pin51=PD1
 Mcu.Pin52=PD2
@@ -177,7 +224,7 @@ Mcu.Pin56=PD6
 Mcu.Pin57=PD7
 Mcu.Pin58=PB3 (JTDO/TRACESWO)
 Mcu.Pin59=PB4 (NJTRST)
-Mcu.Pin6=PC2_C
+Mcu.Pin6=PH1-OSC_OUT (PH1)
 Mcu.Pin60=PB5
 Mcu.Pin61=PB6
 Mcu.Pin62=PB7
@@ -186,12 +233,11 @@ Mcu.Pin64=PE0
 Mcu.Pin65=PE1
 Mcu.Pin66=VP_FREERTOS_VS_CMSIS_V2
 Mcu.Pin67=VP_SYS_VS_tim2
-Mcu.Pin68=VP_TIM1_VS_ClockSourceINT
-Mcu.Pin69=VP_MEMORYMAP_VS_MEMORYMAP
-Mcu.Pin7=PC3_C
-Mcu.Pin8=PA0
-Mcu.Pin9=PA1
-Mcu.PinsNb=70
+Mcu.Pin68=VP_MEMORYMAP_VS_MEMORYMAP
+Mcu.Pin7=PC1
+Mcu.Pin8=PC2_C
+Mcu.Pin9=PC3_C
+Mcu.PinsNb=69
 Mcu.ThirdPartyNb=0
 Mcu.UserConstants=
 Mcu.UserName=STM32H750VBTx
@@ -226,6 +272,7 @@ MxCube.Version=6.13.0
 MxDb.Version=DB.6.0.130
 NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
 NVIC.DMA1_Stream0_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
+NVIC.DMA1_Stream1_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
 NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
 NVIC.EXTI15_10_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true
 NVIC.ForceEnableDMAVector=true
@@ -394,16 +441,20 @@ PE11.Locked=true
 PE11.Signal=GPIO_Output
 PE12.Locked=true
 PE12.Signal=GPIO_Output
-PE13.Locked=true
-PE13.Signal=S_TIM1_CH3
-PE14.Locked=true
-PE14.Signal=S_TIM1_CH4
 PE15.Locked=true
 PE15.Signal=GPIO_Output
 PE2.GPIOParameters=GPIO_Speed
 PE2.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
 PE2.Mode=Single Bank 1
 PE2.Signal=QUADSPI_BK1_IO2
+PE3.GPIOParameters=GPIO_PuPd
+PE3.GPIO_PuPd=GPIO_PULLDOWN
+PE3.Locked=true
+PE3.Signal=GPIO_Input
+PE4.GPIOParameters=GPIO_PuPd
+PE4.GPIO_PuPd=GPIO_PULLDOWN
+PE4.Locked=true
+PE4.Signal=GPIO_Input
 PE7.Signal=FMC_D4_DA4
 PE8.Signal=FMC_D5_DA5
 PE9.Signal=FMC_D6_DA6
@@ -442,7 +493,7 @@ ProjectManager.ToolChainLocation=
 ProjectManager.UAScriptAfterPath=
 ProjectManager.UAScriptBeforePath=
 ProjectManager.UnderRoot=true
-ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_MDMA_Init-MDMA-false-HAL-true,4-MX_DMA_Init-DMA-false-HAL-true,5-MX_ADC1_Init-ADC1-false-HAL-true,6-MX_DAC1_Init-DAC1-false-HAL-true,7-MX_FMC_Init-FMC-false-HAL-true,8-MX_I2C1_Init-I2C1-false-LL-true,9-MX_QUADSPI_Init-QUADSPI-false-HAL-true,10-MX_SPI2_Init-SPI2-false-HAL-true,11-MX_TIM1_Init-TIM1-false-HAL-true,12-MX_USB_OTG_FS_PCD_Init-USB_OTG_FS-false-HAL-true,false-13-MX_SDMMC2_SD_Init-SDMMC2-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true
+ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_MDMA_Init-MDMA-false-HAL-true,4-MX_DMA_Init-DMA-false-HAL-true,5-MX_ADC1_Init-ADC1-false-HAL-true,6-MX_DAC1_Init-DAC1-false-HAL-true,7-MX_FMC_Init-FMC-false-HAL-true,8-MX_I2C1_Init-I2C1-false-LL-true,9-MX_QUADSPI_Init-QUADSPI-false-HAL-true,10-MX_SPI2_Init-SPI2-false-HAL-true,11-MX_USB_OTG_FS_PCD_Init-USB_OTG_FS-false-HAL-true,false-12-MX_SDMMC2_SD_Init-SDMMC2-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true
 QUADSPI.ClockPrescaler=0
 QUADSPI.DeviceType=SPI_DEVICE_FLASH
 QUADSPI.FifoThreshold=4
@@ -573,22 +624,12 @@ SH.FMC_NWE.0=FMC_NWE,Lcd1
 SH.FMC_NWE.ConfNb=1
 SH.GPXTI15.0=GPIO_EXTI15
 SH.GPXTI15.ConfNb=1
-SH.S_TIM1_CH3.0=TIM1_CH3,PWM Generation3 CH3
-SH.S_TIM1_CH3.ConfNb=1
-SH.S_TIM1_CH4.0=TIM1_CH4,PWM Generation4 CH4
-SH.S_TIM1_CH4.ConfNb=1
 SPI2.CalculateBaudRate=24.0 MBits/s
 SPI2.DataSize=SPI_DATASIZE_8BIT
 SPI2.Direction=SPI_DIRECTION_2LINES
 SPI2.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,DataSize
 SPI2.Mode=SPI_MODE_MASTER
 SPI2.VirtualType=VM_MASTER
-TIM1.Channel-PWM\ Generation3\ CH3=TIM_CHANNEL_3
-TIM1.Channel-PWM\ Generation4\ CH4=TIM_CHANNEL_4
-TIM1.IPParameters=Channel-PWM Generation3 CH3,Channel-PWM Generation4 CH4,Pulse-PWM Generation3 CH3,Period,Prescaler
-TIM1.Period=255
-TIM1.Prescaler=16
-TIM1.Pulse-PWM\ Generation3\ CH3=127
 USB_OTG_FS.IPParameters=VirtualMode
 USB_OTG_FS.VirtualMode=Device_Only
 VP_FREERTOS_VS_CMSIS_V2.Mode=CMSIS_V2
@@ -597,8 +638,6 @@ VP_MEMORYMAP_VS_MEMORYMAP.Mode=CurAppReg
 VP_MEMORYMAP_VS_MEMORYMAP.Signal=MEMORYMAP_VS_MEMORYMAP
 VP_SYS_VS_tim2.Mode=TIM2
 VP_SYS_VS_tim2.Signal=SYS_VS_tim2
-VP_TIM1_VS_ClockSourceINT.Mode=Internal
-VP_TIM1_VS_ClockSourceINT.Signal=TIM1_VS_ClockSourceINT
 board=custom
 rtos.0.ip=FREERTOS
 rtos.0.tasks.0=allocationType,Dynamic;bufferName,NULL;codeGen,Default;controlBlockName,NULL;entry,StartDefaultTask;name,defaultTask;parameter,NULL;priority,osPriorityNormal;stackSize,128