mirror of
https://gitlab.com/zephray/glider.git
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107 lines
2.9 KiB
C
107 lines
2.9 KiB
C
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//
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// Copyright 2022 Wenting Zhang <zephray@outlook.com>
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy
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// of this software and associated documentation files (the "Software"), to deal
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// in the Software without restriction, including without limitation the rights
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// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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// copies of the Software, and to permit persons to whom the Software is
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// furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in
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// all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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// SOFTWARE.
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//
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#include "pico/stdlib.h"
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#include "fpga.h"
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#include "bitstream.h"
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#define FPGA_CS 12
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#define FPGA_MOSI 13
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#define FPGA_MISO 14
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#define FPGA_SCLK 15
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#define FPGA_PROG 17
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#define FPGA_DONE 18
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#define FPGA_SUSP 19
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static int fpga_done = 0;
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static void gpio_init_out(uint32_t pin, bool val) {
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gpio_init(pin);
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gpio_put(pin, val);
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gpio_set_dir(pin, GPIO_OUT);
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}
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static void gpio_init_ipu(uint32_t pin) {
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gpio_init(pin);
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gpio_pull_up(pin);
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}
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static void delay_loop(uint32_t t) {
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volatile uint32_t x = t;
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while (x--);
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}
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static void fpga_send_byte(uint8_t byte) {
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for (int i = 0; i < 8; i++) {
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gpio_put(FPGA_MOSI, byte & 0x80);
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gpio_put(FPGA_SCLK, 1);
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byte <<= 1;
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gpio_put(FPGA_SCLK, 0);
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}
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}
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static void fpga_load_bitstream(uint8_t *stream, int size) {
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gpio_put(FPGA_CS, 0);
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for (int i = 0; i < size; i++) {
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fpga_send_byte(stream[i]);
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}
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gpio_put(FPGA_CS, 1);
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for (int i = 0; i < 1000; i++) {
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if (gpio_get(FPGA_DONE) == 1)
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break;
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sleep_ms(1);
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}
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if (gpio_get(FPGA_DONE) == 0) {
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fatal("FPGA done does not go high after 1s");
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}
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else {
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printf("FPGA bitstream load done.");
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}
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}
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void fpga_init(void) {
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// Initialize FPGA pins
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gpio_init_out(FPGA_CS, 1);
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gpio_init_out(FPGA_MOSI, 1);
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gpio_init_ipu(FPGA_MISO);
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gpio_init_out(FPGA_SCLK, 0);
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gpio_init_out(FPGA_PROG, 1);
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gpio_init_ipu(FPGA_DONE);
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gpio_init_out(FPGA_SUSP, 0);
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// FPGA Reset
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gpio_put(FPGA_PROG, 0);
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sleep_ms(100);
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gpio_put(FPGA_PROG, 1);
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sleep_ms(100);
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// Load bitstream
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fpga_load_bitstream(fpga_bitstream, fpga_bitstream_length);
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}
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void fpga_suspend(void) {
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}
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void fpga_resume(void) {
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}
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