200 lines
5.6 KiB
Diff
200 lines
5.6 KiB
Diff
From ba17588a940ee712c3ef6d458adb1087f0c84521 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Timo=20Ter=C3=A4s?= <timo.teras@iki.fi>
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Date: Thu, 5 Feb 2015 09:28:10 +0200
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Subject: [PATCH] backport changes from upstream padlock module.
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Includes support for VIA Nano 64-bit mode.
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Signed-off-by: Timo Teräs <timo.teras@iki.fi>
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---
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engines/e_padlock.c | 142 +++++++++++++++++++++++++++++++++++++++++++++-------
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1 file changed, 125 insertions(+), 17 deletions(-)
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diff --git a/engines/e_padlock.c b/engines/e_padlock.c
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index 2898e4c..94406cb 100644
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--- a/engines/e_padlock.c
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+++ b/engines/e_padlock.c
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@@ -101,7 +101,10 @@
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*/
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# undef COMPILE_HW_PADLOCK
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# if !defined(I386_ONLY) && !defined(OPENSSL_NO_INLINE_ASM)
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-# if (defined(__GNUC__) && (defined(__i386__) || defined(__i386))) || \
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+# if (defined(__GNUC__) && __GNUC__>=2 && \
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+ (defined(__i386__) || defined(__i386) || \
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+ defined(__x86_64__) || defined(__x86_64)) \
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+ ) || \
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(defined(_MSC_VER) && defined(_M_IX86))
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# define COMPILE_HW_PADLOCK
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# endif
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@@ -303,6 +306,7 @@ static volatile struct padlock_cipher_data *padlock_saved_context;
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* =======================================================
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*/
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# if defined(__GNUC__) && __GNUC__>=2
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+# if defined(__i386__) || defined(__i386)
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/*
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* As for excessive "push %ebx"/"pop %ebx" found all over.
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* When generating position-independent code GCC won't let
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@@ -379,22 +383,6 @@ static int padlock_available(void)
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return padlock_use_ace + padlock_use_rng;
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}
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-# ifndef OPENSSL_NO_AES
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-# ifndef AES_ASM
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-/* Our own htonl()/ntohl() */
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-static inline void padlock_bswapl(AES_KEY *ks)
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-{
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- size_t i = sizeof(ks->rd_key) / sizeof(ks->rd_key[0]);
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- unsigned int *key = ks->rd_key;
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-
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- while (i--) {
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- asm volatile ("bswapl %0":"+r" (*key));
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- key++;
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- }
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-}
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-# endif
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-# endif
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-
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/*
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* Force key reload from memory to the CPU microcode. Loading EFLAGS from the
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* stack clears EFLAGS[30] which does the trick.
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@@ -448,6 +436,110 @@ static inline void *name(size_t cnt, \
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: "edx", "cc", "memory"); \
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return iv; \
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}
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+#endif
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+
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+#elif defined(__x86_64__) || defined(__x86_64)
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+
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+/* Load supported features of the CPU to see if
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+ the PadLock is available. */
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+static int
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+padlock_available(void)
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+{
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+ char vendor_string[16];
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+ unsigned int eax, edx;
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+
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+ /* Are we running on the Centaur (VIA) CPU? */
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+ eax = 0x00000000;
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+ vendor_string[12] = 0;
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+ asm volatile (
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+ "cpuid\n"
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+ "movl %%ebx,(%1)\n"
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+ "movl %%edx,4(%1)\n"
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+ "movl %%ecx,8(%1)\n"
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+ : "+a"(eax) : "r"(vendor_string) : "rbx", "rcx", "rdx");
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+ if (strcmp(vendor_string, "CentaurHauls") != 0)
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+ return 0;
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+
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+ /* Check for Centaur Extended Feature Flags presence */
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+ eax = 0xC0000000;
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+ asm volatile ("cpuid"
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+ : "+a"(eax) : : "rbx", "rcx", "rdx");
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+ if (eax < 0xC0000001)
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+ return 0;
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+
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+ /* Read the Centaur Extended Feature Flags */
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+ eax = 0xC0000001;
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+ asm volatile ("cpuid"
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+ : "+a"(eax), "=d"(edx) : : "rbx", "rcx");
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+
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+ /* Fill up some flags */
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+ padlock_use_ace = ((edx & (0x3<<6)) == (0x3<<6));
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+ padlock_use_rng = ((edx & (0x3<<2)) == (0x3<<2));
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+
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+ return padlock_use_ace + padlock_use_rng;
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+}
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+
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+/* Force key reload from memory to the CPU microcode.
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+ Loading EFLAGS from the stack clears EFLAGS[30]
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+ which does the trick. */
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+static inline void
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+padlock_reload_key(void)
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+{
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+ asm volatile ("pushfq; popfq");
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+}
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+
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+#ifndef OPENSSL_NO_AES
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+/*
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+ * This is heuristic key context tracing. At first one
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+ * believes that one should use atomic swap instructions,
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+ * but it's not actually necessary. Point is that if
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+ * padlock_saved_context was changed by another thread
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+ * after we've read it and before we compare it with cdata,
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+ * our key *shall* be reloaded upon thread context switch
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+ * and we are therefore set in either case...
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+ */
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+static inline void
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+padlock_verify_context(struct padlock_cipher_data *cdata)
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+{
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+ asm volatile (
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+ "pushfq\n"
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+" btl $30,(%%rsp)\n"
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+" jnc 1f\n"
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+" cmpq %2,%1\n"
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+" je 1f\n"
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+" popfq\n"
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+" subq $8,%%rsp\n"
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+"1: addq $8,%%rsp\n"
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+" movq %2,%0"
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+ :"+m"(padlock_saved_context)
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+ : "r"(padlock_saved_context), "r"(cdata) : "cc");
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+}
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+
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+/* Template for padlock_xcrypt_* modes */
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+/* BIG FAT WARNING:
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+ * The offsets used with 'leal' instructions
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+ * describe items of the 'padlock_cipher_data'
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+ * structure.
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+ */
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+#define PADLOCK_XCRYPT_ASM(name,rep_xcrypt) \
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+static inline void *name(size_t cnt, \
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+ struct padlock_cipher_data *cdata, \
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+ void *out, const void *inp) \
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+{ void *iv; \
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+ asm volatile ( "leaq 16(%0),%%rdx\n" \
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+ " leaq 32(%0),%%rbx\n" \
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+ rep_xcrypt "\n" \
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+ : "=a"(iv), "=c"(cnt), "=D"(out), "=S"(inp) \
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+ : "0"(cdata), "1"(cnt), "2"(out), "3"(inp) \
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+ : "rbx", "rdx", "cc", "memory"); \
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+ return iv; \
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+}
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+#endif
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+
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+#endif /* cpu */
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+
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+
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+# ifndef OPENSSL_NO_AES
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/* Generate all functions with appropriate opcodes */
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/* rep xcryptecb */
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@@ -458,7 +550,23 @@ PADLOCK_XCRYPT_ASM(padlock_xcrypt_ecb, ".byte 0xf3,0x0f,0xa7,0xc8")
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PADLOCK_XCRYPT_ASM(padlock_xcrypt_cfb, ".byte 0xf3,0x0f,0xa7,0xe0")
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/* rep xcryptofb */
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PADLOCK_XCRYPT_ASM(padlock_xcrypt_ofb, ".byte 0xf3,0x0f,0xa7,0xe8")
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+
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+# ifndef AES_ASM
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+/* Our own htonl()/ntohl() */
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+static inline void padlock_bswapl(AES_KEY *ks)
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+{
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+ size_t i = sizeof(ks->rd_key) / sizeof(ks->rd_key[0]);
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+ unsigned int *key = ks->rd_key;
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+
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+ while (i--) {
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+ asm volatile ("bswapl %0":"+r" (*key));
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+ key++;
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+ }
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+}
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+# endif
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+
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# endif
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+
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/* The RNG call itself */
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static inline unsigned int padlock_xstore(void *addr, unsigned int edx_in)
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{
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--
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2.2.2
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